Apparatus for computing power consumption of MOS transistor logi

Details Apparatus for computing power consumption of MOS transistor logi Apparatus for computing power consumption of MOS transistor logi

1993-07-30

1995-12-05

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054735483

ABSTRACT:
Apparatus for computing power consumption in an MOS transistor logic function block include circuit information deriving unit for deriving circuit information appropriate for a logic function block of interest based on input and output varying signals to and from said logic function block, load capacitance data, and a net list, slew rate determining unit for determining an input slew rate based on information from said circuit information deriving unit, a memory section containing expressions for use in computation of power consumption caused by through-current, each expression corresponding to a different one of various types of logic function blocks and representing power consumption caused by through-current as a function of a slew rate and load capacitance, and power consumption determining unit for determining power consumption due to through-current by substituting the slew rate as determined by said slew rate determining unit and load capacitance data into the computation expression as read from said memory section.

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"Electrical Optimization of PLAs" by Hedlund et al., IEEE 22nd Design Automation Conference, 1985, pp. 681-687.
"Optimization of Digital MOS VLSI Circuits" by Mark D. Matson Chapel Hill Conference, 1985, pp. 109-126.
IEEE Transactions On Computer Aided Design Of Integrated Circuits And System, Jun. 1990, pp. 642-654, Chowdhury et al., "Estimation of Maximum Currents in MOS IC Logic Circuits".
Proceedings Of The 1991 Custom Integrated Circuits Conference, May 12, 1991, pp. 8.3.1-8.3.4, Kimura et al., "Calculation of Total Dynamic Current of VLSI Using a Switch Level Timing Simulator (RSIM-FX)".

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