Apparatus for computing delay time of integrated circuit

Details Apparatus for computing delay time of integrated circuit Apparatus for computing delay time of integrated circuit

1994-12-07

1997-09-02

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 1750

Patent

active

056638892

ABSTRACT:
A delay time computing apparatus includes a data base for storing data on various cells, an input device operable by a designer, and a processing unit coupled to the data base and the input device. The processing unit includes a data input interface, a path building section and a delay time computing section. The data input interface controls transfer of input data from the input device. The path building section reads detailed data on a selected cell from the data base in accordance with circuit redesign data input by a circuit designer to the data input device, and thereby constructs a signal propagation path for cells involved in circuit redesign. Every time the path building section constructs new signal propagation paths, the delay time computing section computes delay times of cells involved in circuit redesign.

REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 4947365 (1990-08-01), Masubuchi
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5095454 (1992-03-01), Huang
patent: 5168563 (1992-12-01), Shenoy et al.
patent: 5173864 (1992-12-01), Watanabe et al.
patent: 5210700 (1993-05-01), Tom
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5396435 (1995-03-01), Ginetti
patent: 5422317 (1995-06-01), Hua et al.
patent: 5448497 (1995-09-01), Ashar et al.
patent: 5459673 (1995-10-01), Carmean et al.
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5463563 (1995-10-01), Bair et al.
patent: 5471409 (1995-11-01), Tani
patent: 5500808 (1996-03-01), Wang
Bening et al., "Developments in Logic Network Path Delay Analysis," 1982 19th Design Automation Conference, pp. 605-615.
Donath et al., "Timing Driven Placement Using complete Path Delays", 1990 27th ACM/IEEE Design Automation Conference, pp. 84-89.
Teig et al., "Timing--Driven Layout of Cell-Based ICs," VLSI Systems Design, May 1986, pp. 63-64, 68, 70-73.

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