Apparatus for compensating locking error in high speed...

Details Apparatus for compensating locking error in high speed... Apparatus for compensating locking error in high speed...

1999-12-29

2001-07-03

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06255870

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a delay locked loop (DLL); and, more particularly, to an apparatus for compensating a locking error in a high speed memory device using a delay locked loop (DDL).
DESCRIPTION OF THE PRIOR ART
In generally, a delay lock loop (hereinafter, referred to as a DLL) is a clock recovery circuit for correctly synchronizing a data output, which is outputted from a memory core through an input/output line, with that of an external clock. As shown in
FIG. 1
showing a block diagram of a register-controlled digital DLL, after buffering an external clock through a clock buffer
1
, the buffered clock signal CLK_BUF is divided into several divided clock signals including a first divided clock signal CLK_DIV and a second divided clock signal CLK_COM
2
through a ⅛ divider
5
. Hereinafter, the second divided clock signal CLK_COM
2
is referred to as a second comparing clock signal. A first delay unit
6
receives the first divided clock signal CLK_DIV to generate a delayed clock CLK_DLY. A delay monitor
7
having a modeling of delay value corresponding to a sum of respective delay times of a clock buffer
1
, an output buffer
3
and I/O line
4
receives the delayed clock signal CLK_DLY to generate a first comparing clock signal CLK_COM
1
. Additionally, a phase comparator
8
compares the first comparing clock signal CLK_COM
1
and the second comparing clock signal CLK_COM
2
to generate an output signal PC_OUT to a shift control unit
9
. Meanwhile, the buffered clock signal CLK_BUF from the clock buffer
1
is inputted into a second delay unit
2
and is outputted through an output buffer
3
to an I/O line
4
. Consequently, the output data outputted from the I/O line
4
is synchronized with the external clock signal. At this time, the shift control unit
9
controls the first and second delay units
2
and
6
according to the output signal PC_OUT of the phase comparator
8
and consequently, a DLL clock having a predetermined time delay is generated. That is, a time delay TD_DLY of the first delay unit
6
is gradually increased from a minimum time delay until each phase of the two clock signals CLK
13
COM
1
and CLK_COM
2
inputted into the phase comparator
8
is correctly synchronized with each other.
FIG. 2
is a clock timing chart illustrating a lockable initial operation of the DLL. As shown in
FIG. 2
, at an initial operation of the DLL, a rising edge of the first comparing clock signal CLK_COM
1
should exist within a low level width Tcyc of the second comparing clock signal CLK_COM
2
. That is, the phase of the first comparing clock signal CLK_COM
1
is delayed by gradually increasing the time delay TD_DLY of the first delay unit
6
, to thereby synchronizing the rising edge of the first comparing clock signal CLK_COM
1
with that of the second comparing clock signal CLK_COM
2
.
FIG. 3
is a clock timing chart illustrating an initial operation of the DLL with a locking error. As shown in
FIG. 3
, at an initial clock timing, the phase comparator
8
generates a control signal to precede the phase of the first comparing clock signal CLK_COM
1
, not to delay it. Accordingly, since the first delay unit
6
can not make the delay less than the initial minimum delay, there has been an unlock problem that the first comparing clock signal CLK_COM
1
can not be synchronized with the second comparing clock signal CLK_COM
2
. As the initial time delay TD_DLY of the first delay unit
6
and the time delay TD_MON of the delay monitor
7
are increasing and the low level width Tcyc of the second comparing clock signal CLK_COM
2
are decreasing, such an unlock problem will be greatly increased.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a DLL and more particularly, to an apparatus for compensating a locking error in a high speed memory device using the DLL.
In accordance with an aspect of the present invention, there is provided an apparatus for compensating a locking error in a high speed memory device using a DLL circuit, comprising: a division means for dividing a buffered external clock signal into a plurality of divided clock signals having respective pulse widths, wherein the plurality of the divided clock signals include a first clock signal, a second clock signal corresponding to an inverted first clock signal, and a third clock signal having a low level width twice as wide as that of the second clock signal; a selection means for selecting one of the second clock signal and the third clock signal in response to a first control signal; a delay means for delaying the first clock signal and gradually increasing a time delay in response to a second control signal; a means for receiving and delaying the delayed first clock signal according to a modeling of a delay time to generate a fourth clock signal, wherein the modeling of the delay time corresponds to a delay time from a clock buffer for buffering the external clock signal to an output unit for outputting an internal data; an initial clock control means for generating the first control signal, wherein the first control signal is allowed to select the second clock signal by the selection means in case when a rising edge of the fourth clock signal is disposed within a low level width of the second clock signal, and wherein the first control signal is allowed to select the third clock signal by the selection means in case when a rising edge of the fourth clock signal is disposed outside a low level width of the second clock signal; and a phase comparison means for comparing the fourth clock signal and an output signal of the selection means to generate the second control signal.


REFERENCES:
patent: 4109100 (1978-08-01), Unkauf
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5604468 (1997-02-01), Gillig
patent: 5953534 (1999-09-01), Romer et al.
patent: 6140854 (2000-10-01), Coddington et al.
patent: 08167890 (1996-06-01), None
patent: 08147967 (1996-06-01), None
patent: 09017179 (1997-01-01), None
patent: 10285016 (1998-10-01), None
patent: 10336008 (1998-12-01), None
patent: 11065669 (1999-03-01), None
patent: 11066847 (1999-03-01), None
patent: 11086545 (1999-03-01), None
patent: 11120768 (1999-04-01), None
patent: 11145816 (1999-05-01), None
patent: 11126479 (1999-05-01), None
patent: 11004147 (1999-06-01), None

Affiliated with

Also associated with

Rating

Apparatus for compensating locking error in high speed... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for compensating locking error in high speed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for compensating locking error in high speed... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2566812