Patent
1994-09-30
1998-02-24
Chan, Eddie P.
395405, 395508, G06F 1902
Patent
active
057218846
ABSTRACT:
In a memory-to-memory data transfer apparatus, each of a plurality of memories connected to a memory bus is sequentially selected, and data which occupy predetermined positions in the data read from the selected memory are combined into a set of data. The set of data is sequentially written while addresses in the remaining memory is being updated. Alternatively, a plurality of sets of data are sequentially read out while addresses in a memory are being updated, and data which occupy predetermined positions in the read data are combined into a set of data. The set of data is written while the remaining memories are being sequentially selected. The apparatus may have a plurality of memories connected to a data bus and address generators for generating unique addresses for each of the memories in accordance with a predetermined synchronizing signal. The apparatus, in preferred form, effects transfer of data in thinned-out form or phase-divided form by shifting a generated address or by adding a predetermined value to the address.
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Enokida Miyuki
Ishida Yoshihiro
Mita Yoshinobu
Shishizuka Junichi
Canon Kabushiki Kaisha
Chan Eddie P.
Nguyen Hiep T.
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