Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural oscillators controlled
Reexamination Certificate
1999-02-09
2001-03-20
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural oscillators controlled
C370S503000, C331S049000, C327S141000, C327S144000, C375S376000
Reexamination Certificate
active
06204732
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of communications. More particularly, the invention relates to a method and apparatus for clock signal distribution, with transparent switching between a Clock Distribution Unit (CDU) and a redundant CDU, thereby providing a redundant uninterrupted output clock signal.
BACKGROUND OF THE INVENTION
Several communications systems employ synchronous operations, for which incoming and outgoing data flows, as well as data processing, are controlled by a timing clock. Multiplexing techniques, such as Time Division Multiplexing (TDM), enable the combination of several data channels onto a common channel by using prefixed time slots for each channel. Data reconstruction at the receiver should be synchronized to the multiplexing transmitter for reliable extraction of the desired information. Such synchronization strongly depends on a continuous and uninterrupted clock signal. The clock signal is usually originated at a stable and accurate oscillator, and is distributed to any required component by a plurality of CDUs. Therefore, a backup clock distribution circuit should be provided and held in standby mode, to function instead of the original circuit, whenever a failure is detected. Such failures may comprise a lost clock signal, reduction in its power level, frequency instabilities, changes of pulse width, etc.
A known method for providing a continuous clock signal to each desired point is to employ a pair of CDUs which consists of an active CDU and an additional redundant CDU. The output of each CDU is connected to a corresponding input of a selecting switch, which normally transfers the output of the active CDU to the output of the switch, connected to the desired circuitry or component which utilizes the clock signal. Whenever a failure is detected, the selecting switch selects the redundant CDU output and transfers it to its output. The switching operation between the two clock signals should be transparent to the circuitry (the load), fed by the clock signal. Therefore, the two clock signals should be continuously coherent, otherwise switching may cause phase discontinuities and undesired bit transitions. In addition, since the input (reference) signal should also be distributed to other circuits via auxiliary clock outputs, it is required to continuously keep the auxiliary clock signals of the active and redundant CDUs coherent, as well.
Phase-Locked-Loops (PLLs) are sometimes used after the selecting switch to smooth these transitions and to remove noise and instabilities from the clock signal. However, this solution is still problematic, since when using a single PLL and splitting the filtered clock signal, jitter and noise are accumulated along the clock signal path. This requires using such PLL circuitry in each input of a circuitry or component which utilizes the clock signal, and is therefore, costly. Moreover, even when using such plurality of PLLs, each of which smoothes incoming transients, during a long term, a phase difference will be developed, and perfect coincidence will not be obtained.
U.S. Pat. No. 4,282,493 discloses a clock signal generator for providing redundant clock signals, which comprises a master clock module and a slave clock module. The master and slave clock modules are always phase and frequency locked to one another. Upon detecting malfunction, the master is switched automatically or externally, between the clock modules. However, this construction is cumbersome, since each module comprises two PLL oscillators. In addition, this construction lacks the capability of separately controlling the response time of the locking circuitry, which causes smoother transition, and is not designed for the distribution of an externally fed clock signal, or of a higher frequency clock signal, based on a low frequency input signal.
U.S. Pat. No. 4,672,299 discloses a clock circuit which employs PLL circuits to synchronize between two input signals. During normal operation mode, the clock circuit is locked to one input signal. When switching to the other input signal, the PLL divider is controlled to force the loop phase to be matched to the phase of the newly selected input signal. However, this clock is not continuously synchronized to an input signal, but rather provides a phase correction in response to a phase error.
U.S. Pat. No. 5,422,915 discloses a fault tolerant CDU for providing synchronized clock signals to multiple circuit loads, which comprises oscillator circuitry, synchronization circuitry, selection circuitry and distribution circuitry, arranged in redundant form, so that partial failure will not result in total distribution failure. However, this CDU is complex and comprises a plurality of redundant sub-circuit. In addition, all redundant clock signals are locked to a reference signal, with no adaptation capability to be locked to each other.
U.S. Pat. No. 5,355,090 discloses a redundant clock system, generating active and standby clock signals in phase with one another through a pair of substantially identical cross-connected phase corrector circuits. Timing errors are reduced by causing all clock bus interface circuits to activate a standby corrector circuit and to cause the previously active standby corrector circuit to operate in standby mode. This system, however, requires two bus interface circuits and lacks adaptive operation of its employed PLLs to different requirements of response time.
All the methods described above have not yet provided satisfactory solutions to the problem of transparent switching between a Clock Distribution Unit (CDU) and a redundant CDU, while providing a redundant uninterrupted clock signal.
It is an object of the present invention to provide a method and apparatus for clock signal distribution with transparent switching between a Clock Distribution Unit (CDU) and a redundant CDU, which overcomes the drawbacks of prior art.
It is another object of the present invention to provide a method and apparatus for clock signal distribution, with transparent switching between a Clock Distribution Unit (CDU) and a redundant CDU, while keeping their corresponding clock signals continuously coherent.
It is still another object of the present invention to provide a method and apparatus for clock signal distribution with transparent switching between a Clock Distribution Unit (CDU) and a redundant CDU, with adaptive response time of their corresponding loop filters.
Other objects and advantages of the invention will become apparent as the description proceeds.
SUMMARY OF THE INVENTION
The invention is directed to a method for clock signals distribution with continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU. This switching capability is transparent to load circuits which utilize these clock signals. The output clock signals of the CDU and the redundant CDU are continuously kept frequency and phase coherent by generating each output clock signal from a reference signal, using an adaptive PLL circuitry at each CDU, and pre-adjusting the phase of each output clock signal of the redundant CDU to the corresponding output clock signal of the CDU. In the event of a failure in the CDU, the output is taken from the redundant CDU immediately after failure detection.
The PLL in each CDU module can operate with slower or faster response time, in response to a corresponding control signal, and can shift the phase of the generated output clock signal according to a corresponding input signal. Each CDU module can operate in active or standby mode, in response to a corresponding control signal.
Switching capability is provided by a multiplexer, selecting between the output of the active CDU module and the output of the standby CDU module and connecting it to a load circuit, in response to a control signal from a control circuit. The phase of the improved reference frequency output of the clock signal of the standby CDU module is adjusted to the phase of the active CDU module by adding or subtracting an input signal to t
Nachum Emanuel
Rapoport Anatoli
ECI Telecom Ltd
Kinkead Arnold
Lilling & Lilling P.C.
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