Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1997-10-29
1999-09-21
Donaghue, Larry D.
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
711154, 711145, 712 43, G06F 1500
Patent
active
059548126
ABSTRACT:
A microprocessor has an internal cache memory which can cache a mix of normal system memory and system management mode memory. An address translator passes an address unchanged if a system management mode input signal indicates the normal mode. The address translator translates the address to an address range outside a range of addresses occupied by the external memory when in the system management mode. A cache memory is connected to the address translator for caching data with address tags corresponding to an address received from the address translator. The address translator preferably includes an address range comparator comparing the address with a predetermined address range. The address translation may be combined with virtual memory to physical memory address translation. An inverse address translator handles cache line writeback. The inverse address translator includes an inverse address comparator comparing the translated address with the translated address range which generates a match signal for the external system when the cache line writeback address is within the translated address range. The microprocessor may include multiple levels of cache memory with the caches closer to the processor core flushed upon entry into and exit from the system management mode. Address translation and inverse address translation is used for transfers from a unified level two cache and a level one data cache or a level one code cache.
REFERENCES:
patent: 5475829 (1995-12-01), Thome
patent: 5544344 (1996-08-01), Frame
patent: 5603004 (1997-02-01), Kurpanek et al.
patent: 5630087 (1997-05-01), Talluri et al.
patent: 5638532 (1997-06-01), Frame et al.
patent: 5764999 (1998-06-01), Wilcox et al.
Bosshart Patrick W.
Shiell Jonathan H.
Donaghue Larry D.
Donaldson Richard L.
Laws Gerald E.
Marshall, Jr. Robert D.
Texas Instruments Incorporated
LandOfFree
Apparatus for caching system management memory in a computer hav does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for caching system management memory in a computer hav, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for caching system management memory in a computer hav will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-75892