Apparatus for caching smram in an intel processor based computer

Details Apparatus for caching smram in an intel processor based computer Apparatus for caching smram in an intel processor based computer

1994-12-06

1996-08-06

Robertson, David L.

395472, 395483, G06F 1314

Patent

active

055443443

ABSTRACT:
An apparatus and method for caching SMRAM in an Intel.RTM. CPU employing system management mode. A cache for the CPU includes a plurality of data entries and an SMRAM status bit corresponding to each data entry. The SMRAM status bit is set if the data entry holds data in SMRAM, and reset if the data entry does not hold data in SMRAM. The SMRAM status bit distinguishes SMRAM data from system memory data in the cache, thereby eliminating cache coherency problems.

REFERENCES:
patent: 4484267 (1984-11-01), Fletcher
patent: 4885680 (1989-12-01), Anthony et al.
Handy, Jim; The Cache Memory Book; Academic Press, Inc., 1993; p. 86.
IntelDX4.TM. Processor Date Book, (#241944-001), Intel Corp., Feb. 1994; pp. 5-11 through 5-13.

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