Apparatus for bit-parallel addition of binary numbers

Details Apparatus for bit-parallel addition of binary numbers Apparatus for bit-parallel addition of binary numbers

1986-07-10

1989-06-13

Harkcom, Gary V.

Boots, shoes, and leggings

36472417, G06F 750

Patent

active

048398500

ABSTRACT:
In an arrangement for the bit-parallel addition of binary numbers in two's complement form, a series of adders (AD.sub.i) are provided to receive inputs for binary bits of equivalent significance and to emit intermediate sum and carry words which are combined to form result sum words. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, when the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by its carry bit.

REFERENCES:
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patent: 4651296 (1987-03-01), Koike
patent: 4660165 (1987-04-01), Masumoto
Freeman, "Checked Carry Select Adder", IBM Tech. Discl. Bull., vol. 13, No. 6, Nov. 1970, pp. 1504-1505.
Chaudhry et al, "Parallel Binary Adder", IBM Tech. Discl. Bull., vol. 14, No. 5, Oct. 1971, p. 1477.
Williams, "Adder Architecture", IBM Tech. Discl. Bull., vol. 23, No. 10, Mar. 1981, pp. 4587-4590.
K. Hwang, "Computer Arithmetic", (1979), pp. 98-103, John Wiley and Son, New York.
Proceedings of IEEE, vol. 63, No. 4, Apr. 1975, pp. 633-648, Title "Special-Purpose Hardware for Digital Filtering" by Freeny.

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