Apparatus for asserting an end of cycle signal to a processor bu

Details Apparatus for asserting an end of cycle signal to a processor bu Apparatus for asserting an end of cycle signal to a processor bu

1993-03-22

1995-04-04

Bowler, Alyssa H.

Boots, shoes, and leggings

364239, 364DIG1, G06F 1300

Patent

active

054045592

ABSTRACT:
Filtering logic coupled between the microprocessor and the host bus to decode illegal special cycles executed by the processor to prevent these cycles from appearing on the host bus, which would otherwise be misinterpreted by logic coupled to the host bus. In the preferred embodiment, a modularized computer system based primarily on the 80386 or i486 microprocessors by Intel is upgraded to the new P5 or Pentium processor, also by Intel. The host and I/O buses are not modified and operate at the same speed and data width as in the previous systems. A processor board is upgraded with the P5 processor and includes the filtering logic according to the present invention. The P5 processor includes 8 byte enable bits as compared to the 4 byte enable bits used by the microprocessors 80386 and i486. Two new special cycles supported by the P5 processor are not supported by the previous host bus and would cause erroneous operation if allowed to be executed on the host bus. The filtering logic detects the two new cycles and prevents the cycles from being passed to the host bus.

REFERENCES:
patent: 4716527 (1987-12-01), Graciotti
patent: 4779190 (1988-10-01), O'Dell et al.
patent: 5146582 (1992-09-01), Begun
patent: 5159679 (1992-10-01), Culley
patent: 5167026 (1992-11-01), Murray et al.
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5325499 (1994-06-01), Kummer et al.
patent: 5325503 (1994-06-01), Stevens et al.
Intelcorp., Pentium Processor Users Manual, vol. 1: Pentium Processor Data Book-Bus Functional Description, Chapter 6, pp. 6-1 to 6-52, 1993.

Affiliated with

Also associated with

Rating

Apparatus for asserting an end of cycle signal to a processor bu does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for asserting an end of cycle signal to a processor bu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for asserting an end of cycle signal to a processor bu will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2386092