Apparatus for argument reduction in exponential computations of

Details Apparatus for argument reduction in exponential computations of Apparatus for argument reduction in exponential computations of

1993-07-29

1995-10-31

Envall, Jr., Roy N.

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364736, G06F 738

Patent

active

054635748

ABSTRACT:
An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.<1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to "zero" and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS). Also incorporated is a leading zero detector/encoder circuit and a second circuit arrangement operative to perform pipeline operations on exponents connected to an encoder circuit whose output controls the aligner circuit and a selector circuit driven by the outputs of the detector/encoder circuit and encoder circuit whose output controls the normalizer circuit; a xi determining circuit that generates the xi mantissa on a xi-BUS connected to the first circuit arrangement such that: mantissa xi=0=K(1) K(2) 1 0 . . . , 0, and a read-only memory to store the F(xi) values whose output is connected to inputs of the first and second circuits for the respective mantissa and exponent parts of F(xi).

REFERENCES:
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4777613 (1988-10-01), Shahan et al.
patent: 4956799 (1990-09-01), Nakayama
patent: 5042001 (1991-08-01), Brightman et al.
patent: 5235535 (1993-08-01), Nakayama
Tang, "Table-Lookup Algorithms for Elementary Functions and Their Error Analysis", Proceedings 10th IEEE symposium on Computer Arithmetic, pp. 232-236, 1991.
"Vriable-Precision Exponentiation" by P. L. Richman Communications of the Association for Computing Machinery, vol. 16, No. 1, Jan. 1973, New York, N.Y., pp. 38-40.
"Floating-point uP Implements High-Speed Math Functions" by David Quong, EDN Electrical Design News, vol. 31, No. 3, Feb. 1986, Newton, Mass., pp. 143-150.

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