Apparatus for and method of synchronizing a clock signal

Pulse or digital communications – Spread spectrum – Direct sequence

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375111, H04L 700

Patent

active

052590054

ABSTRACT:
The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.

REFERENCES:
patent: 4584695 (1986-04-01), Wong et al.
patent: 4667333 (1987-05-01), Butcher
patent: 4686689 (1987-08-01), Rorden
patent: 4715050 (1987-12-01), Tanaka et al.
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 4953185 (1990-08-01), Goode

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