Coded data generation or conversion – Digital code to digital code converters – Parallel to serial
Patent
1992-07-28
1994-07-05
Williams, Howard L.
Coded data generation or conversion
Digital code to digital code converters
Parallel to serial
370102, H03M 900
Patent
active
053271262
ABSTRACT:
A justifier for parallel justifying data onto a DS-3 mapping includes an input bus for selectively communicating 8 respective I bits simultaneously to the justifier. An output bus receives I, R, O and C bits from the justifier in accordance with the mapping at an eighth of the envelope rate of 44.736 Mb/s. A first data path connected to an input bus via a latch communicates a required number of the I bits to the output bus, during a first cycle of GCLK. A second data path connected to the input bus via the same latch communicates the remainder of the I bits to the output bus over one or more subsequent GCLK cycles to satisfy the mapping. The justifier includes a controller for regulating the flow of the I bits along first and second paths. The controller responds to a first control indicative of the mapping to be followed as provided by a sequencer. The I bits moving along the first and second data paths are received by a triangular multiplexer which selects an appropriate number of the I bits from each path for subsequent transmission to the output bus. A de-justifier, generally complementary in operation to the justifier, de-justifies data from a predetermined mapping. The de-justifier is ideally suited to de-justify data originating from the justifier.
REFERENCES:
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patent: 4669080 (1987-05-01), Aveneau et al.
patent: 4674088 (1987-06-01), Grover
patent: 5030951 (1991-07-01), Eda et al.
patent: 5192950 (1993-03-01), Stephenson
Hewlett--Packard Company
Williams Howard L.
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