Apparatus for and method of measuring cross-correlation...

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system

Reexamination Certificate

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C324S606000, C708S005000, C708S422000

Reexamination Certificate

active

06594595

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a cross-correlation coefficient measurement apparatus and a cross-correlation coefficient measurement method for measuring a cross-correlation coefficient between a plurality of signals each being a repetitive signal like, for example, a clock signal.
For example, if a cross-correlation coefficient &rgr; between a plurality of clock signals in a semiconductor integrated circuit can be measured, how much room of improvement is left to a performance limit (&rgr;=1) of the semiconductor integrated circuit, or how much the semiconductor integrated circuit is degraded from the performance limit can quantitatively be determined. Moreover, a signal-to-noise ratio between the plurality of clock signals can be estimated from the cross-correlation coefficient &rgr;. Measuring only a clock skew cannot provide these solutions.
Conventionally, an estimation of a cross-correlation coefficient between two clock signals has indirectly been performed by measuring a clock skew between these clock signals, and by judging magnitude of an RMS value (root-mean-square value) of the clock skew.
A clock skew has statistically been estimated using a time interval analyzer or a frequency counter. That is, as shown in
FIG. 1
, for example, when a reference clock signal CLK
g
from a clock signal source
11
is distributed and delivered to each of the registers
12
j
and
12
k
, each of the clocks under measurement CLK
j
and CLK
k
in the respective registers
12
j
and
12
k
is inputted to a time interval analyzer
13
, where a timing difference between zero-crossing points of the clock signal under measurement CLK
j
and zero-crossing points of the clock signal under measurement CLK
k
is measured, and a fluctuation of the timing difference is measured by a histogram analysis as a clock skew. An example of clock skew measurement using a time interval analyzer
13
is described in, for example, “Jitter Analysis Clock Solutions”, Wavecrest Corp., 1998.
However, an apparatus for or a method of directly measuring a cross-correlation coefficient between clock signals has not been known yet.
It is an object of the present invention to provide an apparatus and its method that can measure a cross-correlation coefficient between clock signals under measurement.
It is another object of the present invention to provide an apparatus and its method that can estimate not only a cross-correlation coefficient &rgr; between clock signals having the same frequency, but also a cross-correlation coefficient &rgr; between clock signals each having a different frequency from one another.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, an apparatus of the present invention comprises: timing jitter estimators for estimating respective timing jitter sequences of a plurality of signals under measurement; and a cross-correlation coefficient estimator to which the plurality of timing jitter sequences are inputted for calculating a cross-correlation coefficient between the signals under measurement.
According to a second aspect of the present invention, the apparatus of the present invention comprises: timing jitter estimators for estimating respective timing jitter sequences of the plurality of signals under measurement; a skew estimator to which the plurality of timing jitter sequences are inputted for calculating a timing difference sequence between those timing jitter sequences to output a skew sequence between signals; and a cross-correlation coefficient estimation means to which the plurality of timing jitter sequences and the skew sequence between signals are inputted for calculating a cross-correlation coefficient between the signals under measurement.
The principle of the present invention will be explained. In this explanation, a clock signal in a microprocessor is used as a clock signal under measurement.
Clock Skew Measurement Method
First, a clock skew will be defined. As shown in
FIG. 2
, a clock skew is given by the difference between delay times &tgr;
cd
j
and &tgr;
cd
k
of the clock signals. CLK
j
and CLK
k
to arrive at the respective registers
12
j
and
12
k
when the clock signals CLK
j
and CLK
k
are derived from a reference clock signal CLK
g
of a clock signal source
11
as a reference time point of, for example, a clock distribution network. That is, the timing difference is given by an equation (1).
T
Skew
j,k
(
nT
)=&tgr;
cd
k
(
nT
)−&tgr;
cd
j
(
nT
)  (1)
FIG. 3
shows by dotted lines an ideal reference clock signal CLK
g
having a fundamental period T, and ideal clock signals CLK
j
and CLK
k
. Also shown in
FIG. 3
are a difference &tgr;
cd
j
(nT) between an actual rising edge of the reference clock CLK
g
and an actual rising edge of the clock signal CLK
j
, a difference &tgr;
cd
k
(nT) between the rising edge of the reference clock CLK
g
and a rising edge of the clock signal CLK
k
(n=0, 1, 2, . . . ), and the difference between the &tgr;
cd
j
(nT) and &tgr;
cd
k
(nT), i.e., a clock skew T
skew
j,k
(nT).
As shown in
FIG. 4
, it is assumed that rising edges of the clock signals CLK
g
, CLK
j
and CLK
k
occur at time t
cd
g
(nT), t
cd
j
(nT) and t
cd
k
(nT) respectively, and ideal clock edges (clock edge time points when those clock signals do not have their respective jitters) of the clock signals CLK
g
, CLK
j
, and CLK
k
rise at time (nT)
g
, (nT)
j
and (nT)
k
respectively. Then delay time &tgr;
cd
j
(nT) or &tgr;
cd
k
(nT) between the clock depature of the clock signal CLK
j
or CLK
k
and the arrival at the respective registers
12
j
or
12
k
is expressed by the following equation.
τ
c



d
j

(
n



T
)
=


t
c



d
j

(
nT
)
-
t
c



d
g

(
nT
)
=


[
t
c



d
j

(
nT
)
-
(
nT
)
j
]
-
[
t
c



d
g

(
nT
)
-
(
nT
)
g
]
+
{
(
nT
)
j
-
(
nT
)
g
}
=


τ
Skew
g
,
j
+
[
Δ



φ
j

[
n
]

(
T
j
2

π
)
-
Δφ
g

[
n
]

(
T
k
2

π
)
]


[
sec
]
(
2
)
τ
c



d
k

(
n



T
)
=


t
c



d
k

(
nT
)
-
t
c



d
g

(
nT
)
=


[
t
c



d
k

(
nT
)
-
(
nT
)
k
]
-
[
t
c



d
g

(
nT
)
-
(
nT
)
g
]
+
{
(
nT
)
k
-
(
nT
)
g
}
=


τ
Skew
g
,
k
+
[
Δ



φ
k

[
n
]

(
T
k
2

π
)
-
Δφ
g

[
n
]

(
T
g
2

π
)
]


[
sec
]
(
3
)
In this case,
&tgr;
Skew
g,j
=(
nT
)
j
−(
nT
)
g
[sec]  (4)
and
 &tgr;
Skew
g,k
=(
nT
)
k
−(
nT
)
g
[sec]  (5)
are the time difference between an ideal clock edge of the clock signal CLK
j
and an ideal clock edge of the reference clock signal CLK
g
, and the time difference between an ideal clock edge of the clock signal CLK
k
and an ideal clock edge of the reference clock signal CLK
g
, respectively, and those time differences correspond to deterministic components of clock skew (deterministic clock skew values) that are determined by the respective clock signal paths. In addition, &Dgr;&phgr;
g
[n](T
g
/2&pgr;)(=t
cd
g
(nT)−(nT)
g
), &Dgr;&phgr;
j
[n](T
j
/2&pgr;)(=t
cd
j
(nT)−(nT)
j
) and &Dgr;&phgr;
k
[n](T
k
/2&pgr;)(=t
cd
k
(nT)−(nT)
k
) express timing jitter sequences (each unit is second) of the clock signals CLK
g
, CLK
j
and CLK
k
, respectively. When the equations (2) and (3) are substituted in the equation (1), a clock skew T
Skew
j,k
between the clock signal CLK
j
and the clock signal CLK
k
is expressed by the following equation.
T
Skew
j
,
k

[
n
]
=


{
τ
Skew
g
,
k
+
[
Δ



φ
k

[
n
]

(
T
k
2

π
)
-
Δφ
g

[
n
]

(
T
g
2

π
)
]


}
-


{
τ
Skew
g
,
j
+
[
&D

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