Pulse or digital communications – Testing – Phase error or phase jitter
Reexamination Certificate
1999-02-08
2003-09-16
Le, Amanda T. (Department: 2634)
Pulse or digital communications
Testing
Phase error or phase jitter
C324S620000, C702S069000
Reexamination Certificate
active
06621860
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for and a method of measuring a jitter in a microcomputer. More particularly, the present invention relates to an apparatus for and a method of measuring a jitter in a clock generating circuit used in a microcomputer.
2. Description of the Related Art
In the past thirty years, the number of transistors on a VLSI (very large scale integrated circuit) chip has been exponentially increasing in accordance with Moore's law, and the clock frequency of a microcomputer has also been exponentially increasing in accordance with Moore's law. At present time, the clock frequency is about to exceed the limit of 1.0 GHz. (For example, see: Naoaki Aoki, H. P. Hofstee, and S. Dong; “GHz MICROPROCESSOR”, INFORMATION PROCESSING vol. 39, No. 7, July 1998.)
FIG. 1
is a graph showing a progress of clock period in a microcomputer disclosed in Semiconductor Industry Association: “The National Technology Roadmap for Semiconductors, 1997”. In
FIG. 1
, an RMS jitter (root mean square jitter) is also plotted.
In a communication system, a carrier frequency and a carrier phase, or a symbol timing are regenerated by applying non-linear operations to a received signal and by inputting the result of the non-linear process to a phase-locked loop (PLL) circuit. This regeneration corresponds to the maximum likelihood parameter estimation. However, when a carrier or a data cannot correctly be regenerated from the received signal due to an influence of a noise or the like, a retransmission can be requested to the transmitter. In a communication system, a clock generator is formed on a separate chip from the other components. This clock generator is formed on a VLSI chip using a bipolar technology, GaAs technology or a CMOS technology.
In each of many microcomputers, an instruction execution is controlled by a clock signal having a constant period. The clock period of this clock signal corresponds to a cycle time of a microcomputer. (For example, see: Mike Johnson; “Superscale Microprocessor Design”, Prentice-Hall, Inc., 1991.) If the clock period is too short, a synchronous operation becomes impossible and the system is locked. In a microcomputer, a clock generator is integrated in a same chip where other logical circuits are integrated.
FIG. 2
shows, as an example, a Pentium chip. In
FIG. 2
, a white square (□) indicates a clock generating circuit. This microcomputer is produced utilizing a CMOS (complementary metal-oxide semiconductor) processing.
In a communication system, the average jitter or the RMS jitter is important. The RMS jitter contributes to an average noise of signal-to-noise ratio and increases the bit error rate. On the other hand, in a microcomputer, the worst instantaneous value of some parameter determines the operation frequency. That is, the peak-to-peak jitter (the worst value of jitter) determines the upper limit of the operation frequency.
Therefore, for testing of a PLL circuit in a microcomputer, there is required a method of measuring an instantaneous value of jitter accurately and in a short period of time. However, since a measurement of a jitter has been developed in the area of communications, there is no measuring method, in the present state, corresponding to this requirement in the area of microcomputers. It is an object of the present invention to provide a method of measuring an instantaneous value of jitter accurately and in a short period of time.
On the contrary, for testing of a PLL circuit in a communication system, there is required a method of measuring an RMS jitter accurately. Although it takes approximately 10 minutes of measuring time, a measuring method actually exists and is practically used.
FIG. 3
collectively shows comparisons of clock generators between a microcomputer and a communication system.
A phase-locked loop circuit (PLL circuit) is a feedback system. In a PLL circuit, a frequency and a phase &thgr;
i
of a given reference signal are compared with a frequency and a phase &thgr;
0
of an internal signal source, respectively to control the internal signal source, using the differences therebetween, such that the frequency difference or the phase difference can be minimized. Therefore, a voltage controlled oscillator (VCO) which is an internal signal source of a PLL circuit comprises a component or components the delay time of which can be varied. When a DC voltage is inputted to this oscillator, a repetitive waveform having a constant period proportional to the direct current value is outputted.
The PLL circuit relating to the present invention comprises a phase-frequency detector, a charge pump circuit, a loop filter and a VCO.
FIG. 4
shows a basic circuit configuration of a PLL circuit in a block diagram form. Next, the operation of each of the circuit components will be briefly described.
A phase-frequency detector is a digital sequential circuit.
FIG. 5
is a block diagram showing a circuit configuration of a phase-frequency detector comprising two D-type flip-flops D-FF
1
and D-FF
2
and an AND gate. A reference clock is applied to a clock terminal ck of the first D-type flip-flop D-FF
1
, and a PLL clock is applied to a clock terminal ck of the second D-type flip-flop D-FF
2
. A logical value “1” is supplied to each data input terminal D.
In the circuit configuration described above, when each of the two Q outputs of the both flip-flops becomes “1” at the same time, the AND gate resets the both flip-flops. The phase-frequency detector outputs, depending on the phase difference and the frequency difference between the two input signals, an UP signal for increasing the frequency or a DOWN signal for decreasing the frequency. (For example, see: R. Jacob Baker, Henry W. Li, and David E. Boyce; “CMOS Circuit Design, Layout, and Simulation”, IEEE Press, 1998.)
FIG. 6
shows a state transition diagram of a phase-frequency detector (PFD). The phase-frequency detector transits the state by rise edges of a reference clock and a PLL clock. For example, as shown in
FIG. 7
, when the frequency of a reference clock is 40 MHz and the frequency of a PLL clock is 37 MHz, in order to increase the frequency, an UP signal is outputted during a time interval between the two rise edges. A similar operation is also performed when a phase difference is present between the reference clock and the PLL clock. The phase-frequency detector has the following characteristics compared with a phase detector using an Exclusive OR circuit. (For example, see: R. Jacob Baker, Henry W. Li, and David E. Boyce; “CMOS Circuit Design, Layout, and Simulation”, IEEE Press, 1998.)
(i) The phase-frequency detector operates at a rising edge of an input clock, and does not relate to the shape of the waveform such as a pulse width of the clock.
(ii) The phase-frequency detector is not locked by a harmonic of the reference frequency.
(iii) Since both of the two outputs are logical “0” during a time period when the loop is locked, a ripple is not generated at the output of the loop filter.
The phase-frequency detector is highly sensitive to an edge. When an edge of a reference clock cannot be discriminated due to a noise, the phase-frequency detector is hung-up to some state. On the other hand, in a phase detector based on an Exclusive OR circuit, even if an edge cannot be discriminated, the average output is 0 (zero). Therefore,
(iv) the phase-frequency detector is sensitive to a noise.
A charge pump circuit converts logical signals UP and DOWN from the phase-frequency detector (PFD) into specific analog signal levels (i
p
, −i
p
and 0). The reason for the conversion is that, since a signal amplitude in a digital circuit has a large allowance width, a conversion to a specific analog signal level is necessary. (For example, see: Floyd M. Gardner; “Phaselock Techniques”, 2nd edition, John Wiley & Sons, 1979; and Heinrich Meyr and Gerd Ascheid; Synchronization in Digital Communications”, vol. 1, John Wiley & Sons, 1990.)
As shown in
FIG. 8A
, a charge pump circuit
Ishida Masahiro
Soma Mani
Yamaguchi Takahiro
Gallagher & Lathrop
Lathrop, Esq. David N.
Le Amanda T.
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