Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Phase comparison
Reexamination Certificate
2000-01-28
2002-06-04
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Phase comparison
C375S371000, C375S373000, C702S072000
Reexamination Certificate
active
06400129
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for and a method of detecting delay fault in a phase-locked loop circuit, and more particularly, relates to a delay fault detecting apparatus and a delay fault detecting method each of which is suitable for detecting a delay fault in a phase-locked loop (hereinafter referred to as PLL) circuit formed on VLSI (very large scale integrated circuit) chip.
2. Description of the Related Art
A synchronous system performs a cooperative operation by sharing a timing of a clock edge with one another. When a timing of the shared edge is controlled in higher precision, the synchronous system can operate at a higher frequency.
FIG. 1
shows an example of the synchronous system. This system is configured such that a plurality of (in this example, two) VLSI chips
11
and
12
are placed on a single board (not shown). A reference clock &phgr; is supplied to each of the VLSI chips
11
and
12
from a high precision oscillator (for example, a crystal-based clock generator)
13
provided on the board. In PLL circuits
14
and
15
on these VLSI chips, as shown in
FIG. 2
, clocks &phgr;
11
, &phgr;
12
, and &phgr;
21
, &phgr;
22
generated by the on-chip clock generators are synchronized with the externally supplied reference clock &phgr; and are distributed to subsystems
16
and
17
, respectively. (For example, refer to a reference literature d
1
.)
As described above, by synchronizing the edge of an internal clock with respect to the edge of a reference clock, data can be sent and received freely between different chips. By aligning the frequency and the phase of an oscillation waveform of a voltage-controlled oscillator (hereinafter referred to as VCO) with respect to the frequency and the phase of the external reference clock &phgr;, the PLL circuits
14
and
15
play a role in minimizing a clock skew and ensuring a high speed operation of the system.
As is well known, in a microcomputer, the worst case uncertainty in the instantaneous value (a peak-to-peak jitter or the like) of the clock signal determines the operating frequency of the microcomputer. Accordingly, it is necessary in the microcomputer to surely detect, by testing, such a delay fault that manifest itself as a transient clock skew.
Next, an influence of delay faults in PLL circuits on a system will be discussed.
FIG. 3
shows an example of the PLL circuit. This PLL circuit comprises a phase-to-frequency (phase-frequency) detector
21
, a charge pump circuit
22
, a loop filter
23
, a VCO
24
, and a clock decode and buffer circuit
25
. Now, it is assumed that a delay fault DF
1
is present at the reference clock input of the phase-frequency detector
21
. As shown in
FIG. 4
, a reference clock &phgr;
REF
(indicated by a solid line) applied to the reference clock input of the phase-to-frequency detector
21
of the PLL circuit becomes a skew clock &phgr; (indicated by a dotted line) which has been delayed by a constant time period due to the delay fault DF
1
present at the reference clock input, and is fed into the charge pump circuit
22
of the next stage. In the PLL circuit, an edge of an internal clock &phgr;
1
(indicated by a solid line) is synchronized with respect to the edge of the dotted line clock &phgr; which has been delayed by the constant time period. As a result, a clock skew occurs in response to the delay fault DF
1
. Moreover, the clock skew which is a deviation generated at the reference clock input is not compensated in the PLL circuit and is continued to be held at a constant value. As a result, it appears that a large steady-state deviation remains.
Since this delay fault DF
1
is not a fault of an internal block (internal component) of the PLL circuit, the PLL gets into a synchronous state. Accordingly, it is difficult to detect a delay fault at the reference clock input by testing the internal blocks of the PLL circuit. However, a delay fault of this type can easily be detected by comparing the external reference clock &phgr;
REF
with the internal clock &phgr;
1
.
Next, as shown in
FIG. 5
, it is assumed that a delay fault DF
2
is present at the Up signal input of the charge pump circuit
22
. Due to this delay fault DF
2
, a timing in the charge pump circuit
22
for converting an Up signal outputted from the phase-frequency detector
21
into an analog signal to output the converted analog signal is delayed. Moreover, the delay of the analog signal brings about a timing delay of an oscillation of the VCO
24
. In the next step, the phase-frequency detector
21
compares the edge of the reference clock &phgr;
REF
with the edge of the internal clock &phgr;
1
, and controls the timing of the oscillating frequency of the VCO
24
by using a phase error signal the height of which is proportional to the time interval between the rising edges of these two clock signals. The feedback control is continued until the rising edges of both the clock signals are aligned with each other. Therefore, this delay fault DF
2
appears simultaneously with a state transition and is compensated by the feedback. The delay time is maximized immediately after the state transition. Therefore, as shown in
FIG. 6
, a clock skew is also maximized immediately after the state transition, and it is decreased to zero in multiple consecutive cycles, because a PLL circuit is a feed back system as mentioned above. Thus, a transient skew occurs. Since a time during which a skew occurs is limited, it is hard to detect the transient skew by testing.
As discussed above, when a delay fault DF
1
is present at the reference clock input of the phase-frequency detector
21
, a clock skew having constant time duration occurs. This clock skew is not compensated by the PLL circuit. On the other hand, when a delay fault DF
2
is present at the Up signal input of the charge pump circuit
22
, a large transient clock skew appears associated with a state transition shown in FIG.
7
. This transient clock skew caused by the delay fault DF
2
is compensated by the PLL circuit and approaches to zero. It is to be noted that all of the delay faults in the remaining blocks (in the input end of the loop filter
23
and in the input end of the VCO
24
) of the PLL circuit can be mapped to the delay fault in the input end of the charge pump circuit
22
.
A stuck-at fault testing (for example, refer to a reference literature d
2
) has conventionally been utilized most widely in the verification test and the manufacturing test of VLSI chips. First, the stuck-at fault testing will briefly be explained.
A fault model is a model in which a physical defect is abstracted. When the fault model is used, the operation of a circuit in the presence of faults can easily be simulated using a computer. For example, a state in which an output of a CMOS (complementary metal-oxide semiconductor) inverter keeps taking a logical value “1” can be explained by using a model in which a stuck-at 1 fault is present in the output of the inverter. As a cause of the fault of this type, there can be considered a short-circuit defect between the output of the inverter and the power supply line of V
DD
or a physical open defect that breaks a drain of an nMOS (n-channel metal-oxide semiconductor).
In the testing, a test pattern is applied to primary inputs of a circuit under test and a response pattern of the circuit appearing at primary outputs of the circuit under test is observed. By comparing the response pattern with an expected value pattern in fault-free operation, whether the circuit is faulty or not is checked.
FIG. 8
shows a combinational circuit of a NAND gate ND
1
having no stuck fault and a NAND gate ND
2
having a stuck-at 0 fault (s-a-0). The outputs of both the NAND gates ND
1
and ND
2
are taken out through an OR gate OR
1
as a primary output.
A test pattern which can detect the stuck-at 0 fault in the combinational circuit shown in
FIG. 8
is “110”. That is, as shown in
FIG. 8
, it is this test pattern “110” that is applied to the primary inputs of the
Ishida Masahiro
Soma Mani
Yamaguchi Takahiro
Advantest Corporation
Gallagher & Lathrop
Lathrop, Esq. David N.
Metjahic Safet
Nguyen Vincent Q.
LandOfFree
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