Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Reexamination Certificate
2001-04-06
2002-04-16
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
Reexamination Certificate
active
06373410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method and apparatus for converting a sampling frequency of digital signals. More specifically, the present invention relates to an apparatus for and a method of converting a sampling frequency of digital signals in which sampling frequency of image data is converted, utilizing high speed parallel processing function of a data driven processor.
2. Description of the Background Art
In order to carry out various processings on information signals at a high speed and with a high precision, the information signals are generally converted into digital signals for processings. Image signals transmitting a large amount of information are also subjected to such conversion. The image signals are essentially analog signals, and thus are sampled at a certain sampling frequency for conversion into digital signals. Conversion of the sampling frequency of image signals also processes and transmits a large amount of information.
A conventional example of converting the sampling frequency of digital signals includes an apparatus for converting a sampling frequency of digital signals using a data driven processor disclosed, for example, in U.S. Pat. No. 5,327,125. In a data driven processor
4
, a process proceeds in accordance with the rule that “when input data necessary for executing a certain process are all prepared, and resources including an arithmetic processor, necessary for that process are allocated, the process is executed.”
A data processing apparatus including information processing operation of the data driven processor uses a data transmitting apparatus employing asynchronous handshake method. In such a data transmitting apparatus, a plurality of data transmission paths are connected, and the data transmission paths transmit/receive data transmission request signals and transfer permitting signals indicating whether data transfer is permitted or not, with each other, whereby autonomous data transfer is performed.
FIG. 3
is a block diagram showing a configuration of the data transmission path. Referring to
FIG. 3
, the data transmission path includes self-synchronous type transfer control circuits (hereinafter referred to as C elements)
2
a
to
2
c
, data holding circuits (pipeline registers)
3
a
to
3
c
, and logic circuits
3
d
and
3
e
performing operations and the like on outputs of the data holding circuits. C elements
2
a
to
2
c
include an input terminal CI receiving a transfer request signal from a preceding stage, an output terminal CO issuing a transfer request signal to a succeeding stage, an input terminal RI receiving a transfer permitting signal indicating permission or inhibition of transfer from the succeeding stage, an output terminal RO outputting a transfer request signal to the preceding stage, and a control signal output terminal CP controlling pipeline registers
3
a
to
3
c.
FIGS. 4A
to
4
E are timing charts representing the operation of the C elements shown in FIG.
3
. When the terminal CI (or terminal CO) shown in
FIG. 4A
is at “0”, it represents a state in which the data transfer request is issued to the preceding stage (succeeding stage), and when it is at “1”, it represents the state in which data transfer request is not issued to the preceding stage (succeeding stage). When the terminal RI (or terminal RO) is at “0” as shown in
FIG. 4E
, it represents that the succeeding stage (preceding stage) is in the transfer inhibited state and when it is “1”, it means that the succeeding stage (preceding stage) is in a transfer permitted state. When the terminal CI of a C element changes from “1” to “0”, that is, when data transfer is requested from the preceding stage and transferred, the terminal RO changes from “1” to “0”, whereby further data transfer from the preceding stage is inhibited.
When transfer is completed, the input to the terminal CI changes from “0” to “1”, setting a state in which data transfer request is not issued from the preceding stage, notifying that the setting of data from the preceding stage to the C element of interest has been complete. Accordingly, the terminal RO shown in
FIG. 4B
changes from “0” to “1”, notifying the preceding stage that the next transfer is permitted. When the input to the terminal CI attains to “1” and data transfer request from the preceding stage is stopped, a clock pulse is output from the terminal CP shown in
FIG. 4C
, data are output from pipeline registers
3
a
to
3
c
, and an operation is performed by logic circuits
3
d
and
3
e
. When the terminal CO shown in
FIG. 4D
changes from “1” to “0”, data transfer request is issued to the succeeding stage and the data is transferred to the succeeding stage, the input to the terminal RI changes from “1” to “0”, notifying that the succeeding stage has been set to the transfer inhibited state. In response, the output of the terminal CP is set to “0”, control to the pipeline register is stopped, and thereafter, the terminal CO changes from “0” to “1”, to be set to the state in which data transfer request is not made to the succeeding stage. When the data is stored in the pipeline register of the succeeding stage and further, output to the next logic circuit, terminal RI changes “0” to “1”, whereby the succeeding stage is set to the transfer permitted state. By the repetition of this cycle, the next data is transferred, processing such as an operation is performed, and data is transferred in the self-synchronous system.
FIG. 5
is a block diagram of the data driven type processor having the data transmission path shown in FIG.
3
. Referring to
FIG. 5
, the data driven processor Pe includes a junction unit JNC, a firing control unit FC, a processing unit FP, a program storing unit PS, a branching unit BRN, a plurality of pipeline registers
3
a
to
3
c
and C elements
2
a
to
2
c
. The operation of the C elements
2
a
to
2
c
is as described above.
FIGS. 6A and 6B
represent an input data packet and an output data packet input to and output from the data driven processor Pe shown in FIG.
5
.
The input data packet shown in FIG.
6
A and the output packet shown in
FIG. 6B
include a destination node number field storing a destination node number, a generation number field storing a generation number, an instruction code field storing an instruction code, and a data field storing data. The input image signal is stored in the data storing field. The generation number is an identification number for distinguishing data groups to be processed in parallel from each other. The destination node number is a number for distinguishing input data of the same generation from each other, and indicates a transfer destination of the data packet in the data driven type information processing apparatus. The instruction code is for executing an instruction stored in an instruction decoder.
When the data packet shown in
FIG. 6A
is input to data driven processor Pe, the input packet is first passed through junction unit JNC, transmitted to firing control unit FC, and a data pair is formed between data packets having the same destination node number and the same generation number. More specifically, two different data packets having identical node number and the generation number are detected, and of these two having the same numbers, one data packet is additionally stored in the data field of the other packet, and the resulting data packet is output. The data packet storing the data pair in the data field is transmitted to the operating unit FP. The operating unit FP receives the transmitted data packet as an input, based on the instruction code in the input data packet, performs a prescribed operation on the contents of the data packet, and stores the result of operation in the data field of the data packet. This data packet is transmitted to the program storing unit PS.
The program storing unit PS reads, based on the destination node number of the transmitted data packet, the destination node number of the next rank and the instruction code of the next rank, from
Ishikura Tomoya
Muramatsu Tsuyoshi
Takase Motoki
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