Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1998-01-08
2001-10-23
Donaghue, Larry D. (Department: 2154)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C712S001000
Reexamination Certificate
active
06308316
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for analyzing the operations of a parallel processing system, and particularly, to an apparatus for providing information about parallel processing carried out in a multiprocessor system.
2. Description of the Related Art
To obtain information about parallel processing carried out in a multiprocessor system, a prior art embeds special instructions in an executable program written in a high-level language such as FORTRAN or C and analyzes the output of the special instructions.
Such embedding of special instructions deteriorates the performance of the multiprocessor system. Accordingly, the instructions are optionally embedded during the compilation of a program.
Information about serial processing is obtainable by interrupting a program at regular intervals and by finding the execution address at each interruption. This technique is not applicable to obtaining information about parallel processing.
The embedding of special instructions in an executable program will provide inaccurate information about parallel processing in a multiprocessor system because the executable program with embedded special instructions differs from an actual executable program having no special instructions. In addition, this technique takes several minutes to several hours to repeat compilation for tuning, to increase the work to obtain information about the parallel processing.
SUMMARY OF THE INVENTION
An object of the present invention is to efficiently provide information about parallel processing in a multiprocessor system.
According to the present invention, there is provided an apparatus for analyzing the operations of a parallel processing system having a serial processing state, a redundant parallel processing state, and a parallel processing state, the apparatus carrying out an interrupt process to obtain information about the program executing conditions of the parallel processing system.
The parallel processing system may have a wait function for synchronization. The wait function for synchronization of the parallel processing system may include a barrier synchronization wait function.
The parallel processing system may have a hardware asynchronous transfer function and employ a language capable of using the hardware asynchronous transfer function. The language may be a high-level language. The high-level language may be an extended FORTRAN language.
The apparatus may calculate a parallelization ratio P as P=1−(N×J−A)/(R×(N−1)); where N is the number of processors, J is the number of program master interrupts, A is the number of all interrupts, and R is the number of region master interrupts. The apparatus may calculate a parallel-to-serial speed ratio &bgr; as &bgr;=((N−1)×(R−J))/(A−J)+1; where N is the number of processors, R is the number of region master interrupts, J is the number of program master interrupts, and A is the number of all interrupts.
Further, according to the present invention, there is also provided a parallel processing system comprising a plurality of processor elements for carrying out parallel processing; a control unit for specifying the plurality of processor elements to be a serial processing state, a redundant parallel processing state, or a parallel processing state; and a network unit, connected to each of the processor elements and the control unit, for linking the processor elements and the control unit; and an information obtaining unit for carrying out an interrupt process to obtain information about the program executing conditions thereof.
The network unit may comprise a crossbar network. Each of the processor elements may comprise a data transfer unit for transferring data through the network unit, a main storage unit for storing data, a scalar unit for carrying out a scalar calculation, and a vector unit for carrying out a vector calculation. The scalar unit may include an interval timer for carrying out interrupt processing, and a clock for providing interrupt time. The control unit may comprise a general processor for compiling a program read out from a disk unit, a system storage unit for storing system data, and a control processor for controlling the processor elements to actually execute the program.
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Hashimoto Shin
Masaki Reiji
Donaghue Larry D.
Fujitsu Limited
Staas & Halsey , LLP
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