Apparatus for analyzing a substrate employing a copper...

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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C438S687000, C205S118000

Reexamination Certificate

active

06919214

ABSTRACT:
An apparatus for analyzing a substrate employing a copper decoration includes a bath having at least two receiving containers for receiving electrolytes, slots formed at insides of the receiving containers for receiving substrates to be analyzed in a direction that is normal to a bottom face of the bath, lower copper plates provided in the receiving containers, the lower copper plates making contact with entire rear faces of the substrates received in the receiving containers, upper copper plates provided in the receiving containers, each of the upper copper plates corresponding to a respective one of the lower copper plates, and separated from front faces of the substrates, and a power source connected to the upper copper plates and the lower copper plates for providing voltages to the same. A plurality of substrates may be simultaneously analyzed using one apparatus thereby greatly reducing an amount of time required for the analysis.

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patent: 6773573 (2004-08-01), Gabe et al.
patent: 2001/0016420 (2001-08-01), Chou
patent: 1001899940000 (1990-01-01), None
Shin et al. “Influence of Cu-decoration to Individual Crystal Originated Pits on Si Wafer”, Japanese Journal of Applied Physics, vol. 42, pp. 4187-4192, Jul. 2003.
Itsumi et al., “Gate Oxide Defects in MOSLISIs and Octahedral Void Defects in Czochralski Silicon” Japanes Journal of Applied Physics, vol. 37, pp 1228-1235, Mar. 1998.
Park et al., “Nature of Surface and Bulk Defect Induced by Low Dose Oxygeng Implantation in Separation by Implanted Oxygen Wafers”, Japanese Journal of Applied Physics, vol., 40, pp. 2178-2185, Apr. 2001.

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