Apparatus for alternately activating a multiplier and a match un

Details Apparatus for alternately activating a multiplier and a match un Apparatus for alternately activating a multiplier and a match un

1995-03-14

1996-11-26

Swann, Tod R.

Boots, shoes, and leggings

364736, 395375, 371 251, 382 34, G06F 938, G06F 1500

Patent

active

055795277

ABSTRACT:
A processor for use in a parallel computing system. The processor contains: a memory for storing operand values; an arithmetic logic unit (ALU) for performing arithmetic logic operations on operand values; a multiplier, separate from the ALU and coupled to the memory, for generating arithmetic products of a first operand value and a second operand values; and a match unit, separate from the ALU and coupled to the memory, for detecting matches between a predetermined bit pattern and a sequence of bits retrieved from the memory. The match unit also generates a count value indicating a number of detected matches between the predetermined bit pattern and subsequences of bits within the sequence of bits. The first operand value contains the bit pattern and the second operand contains the sequence of bits.

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