Apparatus for allowing external control of local bus read using

Details Apparatus for allowing external control of local bus read using Apparatus for allowing external control of local bus read using

1990-06-06

1993-01-12

Eng, David Y.

Boots, shoes, and leggings

3649278, 3642328, G06F 1300

Patent

active

051797135

ABSTRACT:
A single semiconductor chip containing both I/O bus controller and DRAM controller functions. A single pin on the chip is used to provide both a zero wait state input to the I/O bus controller and to provide a local bus access (LBA) signal for inhibiting both the I/O bus controller and the DRAM controller when an external device is doing an I/O or memory operation on the local bus. Logic isprovided to produce an inhibit signal to the I/O bus controller in response to the LBA signal. Another logic circuit is provided to inhibit the DRAM controller in response to the LBA signal only when there is a memory cycle signal from the microprocessor. The use of the single pin is possible since the zero wait state isgnal will only appear during the latter part of an I/O or memory cycle, which is mutually exclusive with the start of an I/O or memory cycle, which is the only time the LBA signal will appear.

REFERENCES:
patent: 4228520 (1980-10-01), Letteney
patent: 4466055 (1984-08-01), Kinoshita
patent: 4721868 (1988-01-01), Cornell
patent: 4991085 (1991-02-01), Pleva

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