Apparatus for aligning the operation of a plurality of processor

Details Apparatus for aligning the operation of a plurality of processor Apparatus for aligning the operation of a plurality of processor

1990-05-29

1993-06-22

Kulik, Paul V.

Excavating

395800, 371 36, 364DIG1, 3642287, 364229, 3642291, 3642624, 3642627, 364271, 3642712, 3642713, 3642813, G06F 1516

Patent

active

052222373

ABSTRACT:
A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting information to these units. Alignment is achieved by inserting in the instruction stream from each processor that is to be aligned a request for alignment, by testing for prior completion of any instructions that must be completed and by causing all processors to wait until they have all made the request for alignment and completed necessary prior instructions. The alignment unit associated with each processor monitors the instruction stream to detect a request for alignment. The logic network illustratively is an array of AND gates that tests each alignment unit to determine if it has detected a request for alignment. When all the units have made such a request, the logic network informs the alignment units; and the alignment units inform the processors.

REFERENCES:
patent: 3651482 (1972-03-01), Benson et al.
patent: 3753234 (1973-08-01), Gilbert et al.
patent: 3810119 (1974-05-01), Zieve et al.
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4330826 (1982-05-01), Whiteside et al.
patent: 4392196 (1983-06-01), Glenn et al.
patent: 4394725 (1983-06-01), Bienvenu et al.
patent: 4399504 (1983-08-01), Obermarck et al.
patent: 4554626 (1985-11-01), Katz et al.
patent: 4598400 (1986-07-01), Hillis
patent: 4663708 (1987-05-01), Taub
patent: 4733353 (1988-03-01), Jaswa
patent: 4775934 (1988-10-01), Houri et al.
patent: 4833638 (1989-05-01), Vollaro
patent: 5056000 (1991-10-01), Chang
"The Piecewise Data Flow Architecture: Architectural Concepts" by Requa and McGraw, IEEE Transactions on Computers, vol. C-32, No. 5--May 1983.
P. Tang et al., "Processor Self-Scheduling for Multiple-Nested Parallel Loops," Proc. Int'l. Conf. on Parallel Processing, Aug. 1986, pp. 528-535.
R. Gupta, "The Fuzzy Barrier: A Mechanism for High Speed Synchronization of Processors," Proc. Third Int'l. Conf. on Architectural Support for Programming Languages and Operating Systems, Apr. 1989, pp. 54-63.

Affiliated with

Also associated with

Rating

Apparatus for aligning the operation of a plurality of processor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for aligning the operation of a plurality of processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for aligning the operation of a plurality of processor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1446648