Apparatus for aligning and padding data on transfers between dev

Details Apparatus for aligning and padding data on transfers between dev Apparatus for aligning and padding data on transfers between dev

1996-02-01

1996-12-31

Ray, Gopal C.

395853, 395307, G06F 1200, G06F 1300

Patent

active

055903789

ABSTRACT:
A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

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patent: 5148539 (1992-09-01), Enomoto et al.
patent: 5263139 (1993-11-01), Testa et al.
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patent: 5280598 (1994-01-01), Osaki et al.
patent: 5388227 (1995-02-01), McFarland
patent: 5394528 (1995-02-01), Kobayashi et al.

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