Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-12-10
2004-05-25
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S379000, C327S382000
Reexamination Certificate
active
06741114
ABSTRACT:
RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 2001-25523 filed on May 10, 2001, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for adjusting finely the input capacitance of a semiconductor device without increasing a layout area of the device, and to a method of fabricating the apparatus.
2. Discussion of the Related Art
FIG. 1
illustrates a block diagram of an input part
5
of a semiconductor memory device according to a related art. As shown in
FIG. 1
, the input part
5
includes an input pad
10
for transmitting an input signal IN as a signal A, an Electro-Static Discharge (ESD) protection circuit
20
for limiting a passage of ESD as it transmits the signal A to protect the internal circuitry of the memory device, an input buffer
30
for outputting a signal B by converting the level of an output signal of the ESD protection circuit
20
into an appropriate internal logic level of the memory device, and a controller & memory cell array
40
for producing an internal operation signal OUT based on the output signal B of the input buffer
30
. These components of the input part
5
are implemented on a chip.
FIG. 2
illustrates a detailed circuit diagram of the ESD protection circuit
20
and the input buffer
30
shown in FIG.
1
. As shown in
FIG. 2
, the ESD protection circuit
20
is constructed with a resistor R
1
connected between an input node Nd
1
and an output node Nd
2
, and an NMOS type transistor N
1
connected between the output node Nd
2
and a ground voltage Vss. As the drain and the gate of the transistor N
1
are connected together, the transistor N
1
acts as a diode. The input node Nd
1
receives the output signal A of the input pad
10
. The input buffer
30
includes a buffer
32
connected between the output node Nd
2
and the controller and memory cell array
40
for generating and outputting the signal B to the controller & memory cell array
40
.
The input capacitance at an input stage of the semiconductor device varies depending on a junction capacitance Cj at a P-N junction of the NMOS transistor N
1
of the ESD protection circuit
20
connected to the input stage and depending on a gate capacitance Cg of the input buffer
30
connected to the input stage. Since the input capacitance affects the operation of the semiconductor device, the ESD protection circuit
20
and input buffer
30
are generally designed to provide a desired input capacitance for the semiconductor device.
However, even if all the input parts have been designed to provide the desired input capacitance for the semiconductor device, the input capacitance considered outside a chip is different in accordance with input pins which thwarts this effort for obtaining the desired input capacitance. Due to the length difference in a lead-frame and a bonding wire between the input pins in a semiconductor package, input capacitance varies from 7 to 10% depending on the input pins. This causes a significant difference between the operational characteristics of different input pins, which degrades the operation and performance of the semiconductor device.
To overcome this problem, a circuit for adjusting the input capacitance of the input pins has been proposed. However, in this case, the layout area of the semiconductor device is increased due to the addition of this new circuit. This increases the overall size of the semiconductor device. Therefore, there is a need for an apparatus for adjusting the input capacitance of the semiconductor device without requiring an additional layout area.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a fine-adjustment circuit and a fabricating method thereof for adjusting the input capacitance of a semiconductor device that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a fine-adjustment circuit for input capacitance in a semiconductor device that adjusts an input capacitance value of an input node by selectively connecting a plurality of capacitors connected between the input node, which is between an input pad part and an ESD protection circuit part, and a ground voltage.
Another object of the present invention is to provide a method of fabricating a fine-adjustment circuit for input capacitance in a semiconductor memory device that adjusts an input capacitance finely without increasing its layout area by constructing a capacitor with a poly layer/device isolation layer/P-type substrate and forming the poly layer on the device isolation layer under an input pad.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In connection with the above objectives of the present invention, an input part in a semiconductor memory device is disclosed herewith. In the input part, a fine-adjustment circuit for a capacitance according to the present invention adjusts an input capacitance of a semiconductor memory device and is established under an input pad. An input node corresponds to a connection node between the input pad and an ESD protection circuit.
The input capacitance adjustment circuit includes a plurality of capacitors each of which one end is connected to a ground, and a plurality of option switches for connecting the other ends of the capacitors to the input node or the ground respectively. The capacitor is constructed with a poly layer as a top plate, an isolation layer as a dielectric layer, and a P substrate area as a bottom plate.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, an input part in a semiconductor memory device according to the present invention includes an input pad to which an input signal is input from an external source, an ESD protection circuit for protecting an internal circuit by preventing ESD input through the input pad part, an input buffer for converting an input signal received from the input pad into an internal logic level of the semiconductor memory device, and an input capacitance adjustment circuit established under the input pad so as to adjust an input capacitance of the semiconductor memory device.
In another aspect of the present invention, a method of fabricating a fine-adjustment circuit for an input capacitance in a semiconductor memory device according to the present invention includes the steps of providing a P-type substrate in which first to third device isolation layers are formed, forming an N-type well having a P-type impurity region inside between the first and second device isolation layers and forming an active area to form an N-type MOS transistor between the second and third device isolation layers, forming an oxide layer and a polysilicon layer on the entire structure successively, forming a first area by patterning the oxide and polysilicon layers to remain on the first device isolation layer as well as forming a gate on the active area, forming source/drain regions in the P-type substrate below both lateral sides of the gate by carrying out N-type impurity ion implantation, depositing a first insulating interlayer having a predetermined thickness on the entire structure, forming contact holes by etching predetermined portions of the first insulating interlayer on the drain region, P-type impurity region and first area, forming a first metal line on the entire structure including the contact hole, forming a second area connected to the polysilicon layer of the first area and a predetermined portion of the P-type impurity region and a third area contacted electrically with the P
Hynix / Semiconductor Inc.
Lam Tuan T.
Nguyen Hiep
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