Apparatus for adjusting DC offset voltage

Details Apparatus for adjusting DC offset voltage Apparatus for adjusting DC offset voltage

1989-05-30

1991-01-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307494, 3072964, 3072965, G06G 710, H03K 301

Patent

active

049873270

ABSTRACT:
A CMOS differential amplifier or comparator circuit (100) is provided having minimized DC offset voltage. The circuit includes parallel coupled stages (110, 120, 130, 140, 150, 160) that are selectively controlled by an F.E.T. switch (182). The current through each stage is a function of its FET sizing. The current through the differential amplifier is adjusted by the selectively activated certain stages, which increase the current through differential amplifier (100), thereby adjusting the DC offset. The FETs in each stage are sized differently to allow flexibility in adjusting DC offset voltage.

REFERENCES:
patent: 4360785 (1982-11-01), Schade, Jr.
patent: 4658157 (1987-04-01), McGowan
patent: 4714845 (1987-12-01), Devecchi et al.
patent: 4717888 (1988-01-01), Vinn et al.
patent: 4808848 (1989-02-01), Miller
Article by L. Richard Carley, titled "Trimming Analog Circuits Using Floating-Gate Analog MOS Memory", 1989 IEEE International Solid-State Circuits Conference, Feb. 16, 1989.

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