Apparatus for addressing memory with data word and data block re

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3649378, 3649427, 3649511, 364726, G06F 1202, G06F 7544

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active

050124412

ABSTRACT:
Memory address generation circuitry includes two binary counters for generating addresses for application to an address bus. The least significant bits of one counter are connected to the address bus in bit positions corresponding to the most significant bits of the other counter whereby the two counters increment addresses in opposite directions. The mode of address generation permits addresses for data in normal order, data within data blocks in normal order and data blocks in reverse-bit order, and data within data blocks in bit-reverse order and data blocks in normal order. The circuitry has particular applicability in memory address generation when operating on data with algorithms for FFT operations in one or more dimensions.

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