Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-04-29
2002-08-13
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S684000, C257S666000, C257S698000, C257S693000, C257S692000, C257S690000, C257S796000, C257S686000, C257S685000, C257S723000, C257S797000, C257S777000, C257S673000, C257S788000, C257S730000, C257S787000
Reexamination Certificate
active
06433418
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, a semiconductor device unit and a method of manufacturing a semiconductor device unit, and particularly relates to a semiconductor device, a semiconductor device unit and a method of manufacturing a semiconductor device unit which provides high-density mounting by stacking the semiconductor devices.
A semiconductor device is required to be further miniaturized, to achieve higher operational speed and to be more sophisticated, so as to meet the trend of recent electronic devices. The efficiency in mounting the semiconductor device on a mounting board also needs to be improved.
To achieve the above requirements, a majority of semiconductor devices currently available is of the surface-mounting type in which leads are connected on the surface of the mounting board. Yet, a semiconductor device having higher mounting efficiency is desired.
2. Description of the Related Art
FIG. 1
is a perspective view showing a semiconductor device
1
of the prior art.
FIG. 2
is a cross-sectional diagram of the semiconductor device of the prior art taken along a line A—A in FIG.
1
. The semiconductor device
1
is disclosed in Japanese Patent Laid-Open Application Nos. 63-15453 and 63-15451.
A semiconductor device
1
shown in FIG.
1
and in
FIG. 2
includes a semiconductor chip
2
, a resin package
3
for sealing the semiconductor chip
2
, leads
4
and a stage
7
on which the semiconductor chip
2
is mounted. Each of the leads
4
has one end connected to the semiconductor chip
2
by a wire
5
and the other end exposed from a bottom surface
3
a
of the resin package
3
so as to form an external terminal
6
. In other words, in semiconductor device
1
, all parts of the leads
4
except the external terminals
6
are sealed within the package
3
.
In the semiconductor device
1
of the above structure, since the parts forming the external terminals
6
are exposed from the bottom surface
3
a
of the resin package
3
, the amount or length of the leads
4
projecting from the side of the package
3
can be reduced. Because of this, the mounting density of the semiconductor device is increased. Also, in the above structure, it is not necessary to bend the projecting part of the lead and thus a mold utilized for bending is no longer required. Therefore various advantages, for example reduction in the manufacturing cost, are expected.
However, there is a problem in the semiconductor device of the prior art. As shown in
FIG. 2
, terminals
4
a
of the leads
4
, which are to be connected by wires, are positioned at the side of the semiconductor chip
2
. Because of this, the package
3
is large in size, and the semiconductor device
1
can not achieve sufficient miniaturization. Ideally, the size of the semiconductor device is miniaturized so as to be substantially the same as the size of the semiconductor chip. Whereas in the semiconductor device
1
of the prior art, the size of the package
3
is more than twice the size of the semiconductor chip
2
.
For a semiconductor device proposed so as to solve the above problem, see Japanese Patent Application No. 4-281951, entitled “Semiconductor Device and Method of Manufacturing Semiconductor Device”.
FIGS. 3A-3B
show a semiconductor device elated to the above Patent Application.
A semiconductor device
10
A shown in
FIGS. 3A-3B
is provided with a semiconductor chip
11
, a resin package
17
for sealing this semiconductor chip
11
and a plurality of leads
14
. Each of the leads
14
has an inner end
14
a
electrically connected to the semiconductor chip
11
and an outer end exposed from a bottom surface
17
a
of a resin package
17
so as to form an external terminal
16
. All parts of the leads
14
, except the external terminals
16
, are sealed within the package
17
. The semiconductor device
10
A is characterized in that the plurality of the leads
14
is at least partly overlapped with the semiconductor chip
11
vertically within the package
17
.
Because of the above structure, the semiconductor device
10
A is miniaturized compared to the semiconductor device
1
shown in FIG.
1
and
FIG. 2
by an area of the overlapped part (indicated by an arrow L
1
in FIG.
3
A). Also in
FIG. 3A
, the semiconductor device
10
A includes a stage
12
, an electrode pad
13
and wires
15
.
In order to achieve further high-density mounting, semiconductors may be mounted in a vertical stack. However, the semiconductor device
10
A shown in
FIGS. 3A-3B
is not suitable for being mounted vertically in a stack. This causes a problem that further high-density mounting (i.e. three-dimensional mounting) cannot be achieved.
For a semiconductor device proposed so as to solve the above problem, see Japanese Patent Application No. 6-168449, entitled “Semiconductor Device and Semiconductor Device Unit”.
FIGS. 4 and 5
show a semiconductor device related to the above Patent Application.
A semiconductor device
10
B shown in FIG.
4
and in
FIG. 5
includes leads
18
each of which has an inner lead part
18
a
and an outer lead part
18
b
. The semiconductor device is characterized in that a first terminal
18
b
-
1
, a second terminal
18
b
-
2
and a third terminal
18
b
-
c
are formed by extending the outer lead part
18
b
outside the resin package
17
and by bending the outer lead part
18
b
along a shape of the resin package
17
.
The semiconductor device
10
B has a structure such that the first terminal
18
b
-
1
is placed on the bottom surface of the resin package
17
and the second terminal
18
b
-
2
on the top surface of the resin package
17
. Therefore, it is now possible to mount the semiconductor device
10
B in a stack thereby achieving further high-density mounting.
However, the semiconductor device
10
B shown in FIG.
4
and
FIG. 5
is constructed by simply bending the outer lead parts
18
b
along the shape of the resin package
17
so as to pull the outer lead parts
18
b
up to the top surface of the resin package
17
. Because of this, the second terminal parts
18
b
-
2
and the third terminal parts
18
b
-
3
are provided in such a manner that they are slightly spaced apart from the semiconductor device
10
B (see FIG.
5
).
Accordingly, the outer lead parts
18
b
may be easily deformed when an external force is applied. In such a case that neighboring outer lead parts
18
b
are short-circuited, or that the second terminal parts
18
b
-
2
and the third terminal parts
18
b
-
3
are offset from the predetermined position, electric connection between the upper and the lower semiconductor devices
10
B may not be successful. Therefore, there arises a reliability problem in mounting the semiconductor devices in a stack.
In order to solve the above problem, the whole outer lead part
18
b
may be embedded in the resin package
17
. Before being embedded, the outer lead part
18
is bent, for example, by insert-molding. The surface used for electric connection is exposed from the resin package
17
. This structure prevents the outer lead part
18
b
from being unnecessarily displaced from its predetermined position.
However, when the outer lead parts
18
b
are embedded in the resin package
17
, they are not displaced freely within the resin package
17
. For example when there is a temperature rise of the device due to the emission of heat by the semiconductor chip
11
, a stress is produced at an interface between the leads
18
and the resin package
17
. This is caused by the difference in thermal expansion between the leads
18
and the resin package
17
.
The coefficient of thermal expansion of the leads
18
is generally larger than the coefficient of thermal expansion of the resin package
18
. Accordingly, when there is a temperature rise as described above, the leads
18
will press the resin package
17
. Therefore, in the worst case, cracks may be formed in the resin package
17
. Also, when these semiconductor devices are stacked using solder, the above described stress may be a
Fujisawa Tetsuya
Hamano Toshio
Hayashida Katsuhiro
Inoue Hiroshi
Katoh Yoshitsugu
Fujitsu Limited
Williams Alexander O.
LandOfFree
Apparatus for a vertically accumulable semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for a vertically accumulable semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for a vertically accumulable semiconductor device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2921437