Apparatus for a multiple channel direct memory access utilizing

Details Apparatus for a multiple channel direct memory access utilizing Apparatus for a multiple channel direct memory access utilizing

1995-03-08

1997-04-08

Harvey, Jack B.

395847, 395848, 39520007, 395844, 395293, 395287, G06F 304

Patent

active

056197276

ABSTRACT:
An apparatus for multiple channel direct memory access using a virtual array technique comprises n DMA blocks connected in series, each DMA having m independent channels for transferring data. Parameters to control a DMA transfer, such as a source address, destination address, length, and an action mode value, are stored in a memory for each one of the m DMA channels. The first dimension DMA is coupled to the memory to retrieve the parameters and is set in a series mode, while a downstream DMA is set in a normal mode. Operation of the apparatus is begun by starting the first dimension DMA, which then acquires control of the system bus. The first dimension DMA then reads and transfers the DMA parameters to the higher dimension, downstream, DMAs, which preempt control of the system bus away from the first dimension DMA through a multi-layer bus arbiter until the higher dimension DMA transfer is complete. Control of the system bus is then restored to the first dimension DMA.

REFERENCES:
patent: 4514808 (1985-04-01), Murayama et al.
"Direct Memory Access Controller (DMAC) Advance Information" by Motorola Semiconductor Technical Data MC8450, Motorola Inc., 1986, pp. 5-1 through 5-21.
"The Indispensible PC Hardware Book, Your Hardware Questions Answered" by Hans-Peter Messmer, 1994, pp. 376-393.

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