Coded data generation or conversion – Digital code to digital code converters – Substituting specified bit combinations for other prescribed...
Patent
1987-04-23
1988-10-18
Shoop, Jr., William M.
Coded data generation or conversion
Digital code to digital code converters
Substituting specified bit combinations for other prescribed...
375 17, 375 19, H03M 700
Patent
active
047790733
ABSTRACT:
An apparatus converting three bits of binary data (B.sub.1, B.sub.2, B.sub.3) into two ternary symbols (T.sub.1, T.sub.2), in which even numbered pars of the ternary symbols (T.sub.1, T.sub.2), where (T1=T2), are replaced by a pair of ternary symbols (T'.sub.1, T'.sub.2) which do not correspond to any of the three bits of binary data (B.sub.1, B.sub.2, B.sub.3). The replacement occurs when the respective symbols in a respective pair of ternary symbols (T.sub.1, T.sub.2) are in the same ternary level; hence, a run-length of the same symbol can be restricted to four or less. Furthermore, the digital sum variation (DSV) is controlled in every synchronous block which is composed by the above-mentioned replaced output, thereby allowing a 3B-2T code which does not contain a DC component to be obtained. Moreover, inversion or noninversion of the synchronous pattern can be easily determined by distinguishing whether control of the DSV is applied or not to the synchronous block.
REFERENCES:
patent: 4003041 (1977-01-01), Van Duuren et al.
patent: 4408189 (1983-10-01), Betts et al.
Blum Richard K.
Matsushita Electric - Industrial Co., Ltd.
Shoop Jr. William M.
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