Apparatus comprising clock control circuit and device using...

Details Apparatus comprising clock control circuit and device using... Apparatus comprising clock control circuit and device using...

1999-03-18

2002-05-21

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Synchronizers

C365S194000, C365S233100

Reexamination Certificate

active

06393080

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus comprising a clock control circuit which is suitable for synchronous control using high speed clock signals and a device using an internal clock signal synchronized to an external clock signal.
2. Related Art Statement
Recently, a computer system sometimes adopts a clock synchronous type memory, such as a synchronous DRAM, in order to fulfill the requirements for faster processing. A synchronous type memory is designed to use a clock, which is synchronized to a clock signal controlling a memory circuit, also within the memory.
When a delay occurs between a clock signal used within the memory (hereinafter referred to as an internal clock signal) and an external clock signal, such as a clock signal to control the memory circuit, and particularly when the operating speed is high, malfunction is apt to occur in a circuit even when the delay time is small.
Accordingly, a clock control circuit is provided in a semiconductor integrated circuit to synchronize an internal clock signal to an external clock signal.
FIG. 1
is a circuit diagram showing a related art on such a clock control circuit.
FIG. 2
is a waveform diagram illustrating the theory. The circuit in
FIG. 1
adopts an STBD (Synchronous Traced Backwards Delay) as a clock control circuit.
In
FIG. 1
, an external clock signal CK, shown in
FIG. 2
, is inputted to an input terminal
1
. The period of the external clock signal CK is supposed to be &tgr;. This external clock signal CK is taken in through a receiver
2
. The receiver
2
outputs an amplified clock signal CLK after waveform shaping of the external clock signal. When a delay time at the receiver
2
is D
1
, the clock signal CLK outputted from the receiver
2
becomes as shown in
FIG. 2. A
clock control circuit
20
is designed to generate a signal delayed by two periods of the external clock signal thereto.
In order to delay the clock signal CLK by (2&tgr;−D
1
), the clock control circuit
20
, first, generates a pulse FCL, which rises after the time A from the rising timing of the clock signal CLK outputted from the receiver
2
as shown in FIG.
2
. The time from the rising of this pulse FCL to the next rising of the clock signal CLK is, as shown in
FIG. 2
, the time &Dgr; (=&tgr;−A). The clock control circuit
20
measures a time (&tgr;−A), and generates a next pulse RCL after the time 2(&tgr;−A) from the rising of the pulse FCL (see the pulse RCL in FIG.
2
).
As shown in
FIG. 2
, the time from the rising of the pulse RCL to the rising of the next clock signal CLK is &tgr;−&Dgr;=&tgr;−(&tgr;−A)=A. Now, the time from the rising of the pulse RCL to the rising of the external dock signal CK to be inputted next is supposed to be D
2
. When D
2
is a time as shown in
FIG. 2
, an internal clock CK′ (
FIG. 2
) is generated synchronizing to the external clock CK by being delayed by 2 periods to it.
As shown in
FIG. 2
, D
2
is satisfactory so long as it is a value between D
1
and A and has arelation of (D
2
+D
1
)=A. That is, when the time D
2
is a delay time in an outputting stage, it means that an internal clock signal synchronized to the external clock signal can be generated by providing a delay circuit, which operates with the delay time A, the sum of the delay time D
1
due to the receiver
2
and the delay time D
2
in the outputting stage, and providing another delay circuit having a delay time of the time 2 (&tgr;−A).
Next, the operation of a circuit according to a related art will be described with reference to a block diagram shown in
FIG. 1
, waveform diagrams in
FIGS. 3 and 4
, and explanatory views shown in
FIGS. 5
to
8
. Particularly, the operation characteristics of an STBD to store the propagation condition of forward pulse and to control the propagation of rearward pulse corresponding to the stored data is described in detail.
The external clock signal CK having a period &tgr; as shown in
FIG. 3
is inputted to a receiver
2
via an input terminal
1
, and CLK shown in
FIG. 3
is outputted from the receiver
2
. When a delay of the receiver
2
is D
1
, CLK is delayed by D
1
to CK. When no clock control circuit is used, this delay D
1
becomes, as it is, skew of the external clock signal and the internal clock signal. The more the external clock signal becomes high frequency and &tgr; becomes smaller, the more the effect of this skew becomes great. The output signal CLK of the receiver
2
is inputted to an inverter
10
, a control pulse generating circuit
9
and a delay monitor
3
. At the control pulse generating circuit
9
, the control pulse P as shown in
FIG. 3
is generated. In a clock control circuit using an STBD, it is required to initialize all forward-pulse delay circuits before forward pulse is inputted to the first delay unit. By reason of this, a control pulse having a width narrower than the delay time A of a delay monitor
3
is generated, and control is carried out using this control pulse. The output signal FCL of the delay monitor
3
is delayed by A to CLK and inputted to a first forward-pulse delay circuit
5
-
1
of a forward-pulse delay line
5
.
The N-th forward-pulse delay circuit forming a forward-pulse delay line outputs a logical value, which is similar to the output of the (N−1)th forward-pulse delay circuit, to the (N+1)th forward-pulse delay circuit when the control pulse P is “L” and outputs “L” to initialize a forward-pulse delay line
5
when P is “H”.
Output signals of forward-pulse delay circuits are also inputted to state-holding circuits. One of output signals of rearward-pulse delay circuits is also inputted to state-holding circuits. State-holding circuits have two states to take corresponding to signals inputted. The state-holding circuit takes the set state when P is “L” and forward pulse is propagated by the corresponding forward-pulse delay circuit. When P is “H” and rearward pulse is propagated by the corresponding rearward-pulse delay circuit, the state-holding circuit takes the reset state.
An output signal of the state-holding circuit is inputted to a rearward-pulse delay circuit. When the state-holding circuit to which the rearward-pulse delay circuit is connected is in the set state, the N-th rearward-pulse delay circuit inputs a logical value, which is similar to the output of the (N+1)th rearward-pulse delay circuit, to the (N−1)th rearward-pulse delay circuit. When the state-holding circuit connected to the rearward-pulse delay circuit is in the reset state, it outputs a logical value similar to the output of the receiver.
Next, the operation from the input of the forward pulse FCL to a forward-pulse delay line to the output of the output signal RCL from a rearward-pulse delay line is described in detail with reference to
FIGS. 4 and 5
to
8
. Each of
FIGS. 5
to
8
shows the state of t
0
to t
3
in FIG.
4
. Suppose that the delay time of a delay circuit is &Dgr;du, clock period is 10&Dgr;du, the pulse width is 5&Dgr;du, the width A′ of the control pulse P is 2&Dgr;du, the delay time A of the delay monitor is 3&Dgr;du. The set state is expressed with S and the reset state is expressed with R. The numerals marked on delay lines express the output of a delay circuit; “
1
” (=“H”) and “0” (=“L”) (&Dgr;du expresses a delay time per stage of delay circuits).
Now, suppose that, in the initial state at time t
0
, all state-holding circuits are in the reset state R. At this time, as an external clock signal has not been inputted, the output state of all forward-pulse delay circuits and rearward-pulse delay circuits is at “L”(FIG.
5
).
When the forward pulse FCL is inputted to forward-pulse delay circuits, the forward pulse is then propagated by the forward-pulse delay line until the control pulse becomes “H”. As shown in
FIG. 6
, at time t
1
, when the forward pulse F
1
has been propagated up to the 7th stage and the propagation is stopped due to P&a

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