Patent
1996-10-28
1999-10-12
Teska, Kevin J.
G06F 9455, G06F 1750
Patent
active
059665270
ABSTRACT:
A design apparatus, article of manufacture, method and system are disclosed for simulating mass-produced semiconductor device behavior. Drain-to-source current values are obtained from actual semiconductor devices in response to voltage levels at the drain-to-source and gate of a semiconductor device. Semiconductor device attributes, such as channel-length doping concentration are also measured. A device simulator and process simulator are calibrated based upon the actual drain-to-source current values and measured attributes. A process simulator is run in response to simulated process parameters to obtain a plurality of simulated mass-produced semiconductor devices having varying semiconductor attributes. A device simulator is then run using the plurality of simulated mass-produced devices to obtain a plurality of I/V curves based upon the plurality of simulated semiconductor devices. Worst-case I/V curves are then obtained from the plurality of I/V curves by analyzing drain-to-current values in the plurality of I/V curves associated with a predetermined voltage value. Parameters then may be extracted from the worst-case I/V curves in order to determine accurate worst-case semiconductor device designs. Manufacturing guard bands may then also be identified based upon the worst-case I/V curves and idealized I/V curves.
REFERENCES:
patent: 4901242 (1990-02-01), Kotan
patent: 5111404 (1992-05-01), Kotani
patent: 5260865 (1993-11-01), Beauford et al.
patent: 5301118 (1994-04-01), Heck et al.
patent: 5319564 (1994-06-01), Smayling et al.
patent: 5341302 (1994-08-01), Conners et al.
patent: 5402367 (1995-03-01), Sullivan et al.
patent: 5438527 (1995-08-01), Feldbaumer et al.
patent: 5495417 (1996-02-01), Fuduka et al.
patent: 5502643 (1996-03-01), Fujinaga
patent: 5629877 (1997-05-01), Tamegaya et al.
patent: 5646870 (1997-07-01), Krivokapic
Boning, et al., "DOE/OPT: A System for Design of Experiments, Response Surface Modeling & Optimization Using Process & Device Simulation," IEEE Trans on Semiconductor Mfg., vol. 7, Iss. 2, May 1994, pp. 233-244.
Boskin, et al., "A Method for Modeling the Manufacturability of IC Designs," Proc IEEE Int. Conf. On Microelectronics Test Structures, vol. 6, Mar. 1993, p. 241-24.
Dance, et al., "Appl. of yield models for semiconductor yield improvement," Defect & Fault Tolerance on VLSI Systems, 1992 pp. 257-266.
Dill, et al., "Modeling Positive Photoresist," Proceedings of the Kodak Microelectronics Seminar, Oct. 1974, pp. 24-31.
Duvall, "Towards a Practical Methodology for the Statistical Design of Complex IC Products," 1993 VLSI TSA, pp. 112-116.
Heavlin, W.D. and Finnegan, G.P., "Dual Space Algorithms for Designing Space-filling Experiments," Interface 1994, Research Triangle, North Carolina, Jun. 1994, pp. 41-47.
Heavlin, "Variance Components & Computer Experiments," Proc 1994 Amer. Statistical Assoc., pp. 103-108.
Huang, J.H, et al."BSIM3 Manual, version 2.0", Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, 1994 (218 pages).
Iravani, et al., "Statistical Modeling Tools, Methods & Applications for IC Mfg." Proc IEEE '95 Conf on Microelectronic Test Structures, vol. 8 Mar. 1995, pp. 203-207.
Kaplan, S. and Karklin, L., "Calibration of Lithography Simulator by Using Sub-Resolution Patterns," Proceedings on Optical/Laser Microlithography VI, SPIE 1927, pp. 858-867, 1993.
Kizilyalli, et al., "Predictive Worst Case Statistical Modeling of 0.8 .mu.m BICMOS Bipolar Transistors: A Methodology Based on Process & Mixed Device/Circuit Level Simulators," IEEE Trans. On Electron Devices, vol. 40, No. 5, May 1993, pp. 966-973.
Krivokapic, Z. and Heavlin, W. D., "Predicting Manufacturing Variabilities for Deep Micron Technologies: Integration of Process, Device, and Statistical Simulations," in Simulation of Semiconductor Devices and Processes, 5, S Selberherr, H Stippel and E Strasser, eds, pp. 229-232, Springer-Verlag, New York, 1993.
Lopez-Serrano, et al., "Yield Enhancement Prediction with Statistical Process Simulations in an Advanced Poly-emitter Complementary Bipolar Technology," IEEE 1994 Custom IC Cont., pp. 13.1.1(289)-13.1.4(292).
Mack, "Development of Positive Photoresists," Jour. Electro. Chem. Soc: Solid State Sci. & Tech., vol. 134 Issue 1, Jan. 1987, pp. 148-152, Jan. 1987.
Mack, C. and Charrier, E., "Yield Modeling for Photolithography," Proceedings of OCG Microlithography Seminar, pp. 171-182, 1994.
Mandel, "The Statistical Analysis of Experimental Data," John Wiley & Sons, 1964, Chap. 12, pp. 272-311.
Neureuther, et al., "Photoresist Modeling & Device Fabrication Appl.," Optical & Acoustical Microelectronics, 1974, pp. 223-249.
Niu, et al., "A Bayesian Approach to Variable Screening for Modeling the IC Fabrication Process," Circuits & Systems, 1995 IEEE Int'l Symposium, pp. 1227-1230.
Owen, "Controlling Correlations in Latin Hypercube Samples," 1994 Jour. Amer. Statistical Assoc., vol. 89 No. 428, Dec. 1994, pp. 1517-1522.
Pinto, et al., "ULSI Tech. Dev. by Predictive Simulation," 1933 IEEE, pp. 29.1.1-29.1.4.
Rietman, et al., Process Models & Network Complexity, 1993 Int'l. Conf. On Neural Networks, pp. 1265-1269.
Ripley, B.D., Spatial Statistics, pp. 44-74, Wiley, New York, 1981.
Smith, et al., "Comparison of scalar & vector diffraction modeling for deep-UV lithography," SPIE vol. 1927 Optical/Laser Microlithography VI--1993, pp. 847-857.
Stein, "Large Sample Properties of Simulations Using Latin Hypercube Sampling," Technometrics, vol. 29 Iss. 2, May 1987, pp. 143-151.
Welten, et al., "Statistical Worst-Case Simulation for CMOS Technology," IEEE Colloq. No. 153: Improving the Efficiency of IC Mfg. Technology, 1995 (3 pages).
Williams, et al., "Application of Process Statistics to Macro/Behavioral Modeling" IEEE 1993, pp. 515-518.
Heavlin William D.
Krivokapic Zoran
Advanced Micro Devices , Inc.
Mohamed Ayni
Teska Kevin J.
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