Apparatus and systems for VT invariant DDR3 SDRAM write...

Details Apparatus and systems for VT invariant DDR3 SDRAM write... Apparatus and systems for VT invariant DDR3 SDRAM write...

2008-12-19

2010-11-23

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233110, C365S194000

Reexamination Certificate

active

07839716

ABSTRACT:
Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initial write-leveling procedure determines the correct skew and programs a register file in the skew adjustment circuit. The register file includes a register for each of multiple ranks in the DDR3 memory. The values in each register serve to control selection of alignment of the data related signals to align with one of multiple phase shifted versions of a 1× DDR3 clock signal. The phase shifted clock signals are generated by clock divider circuits from a 2× DDR clock signal and use of a single fixed delay line approximating ⅛ of a 1× DDR3 clock period.

REFERENCES:
patent: 7231536 (2007-06-01), Chong et al.
patent: 7477074 (2009-01-01), Pan et al.
patent: 7725755 (2010-05-01), Chong et al.
patent: 2010/0054073 (2010-03-01), Park

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