Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-08-10
2003-03-18
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S786000
Reexamination Certificate
active
06534872
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to device packaging and printed wiring boards, in general, and, more particularly, to placement of vias and signal traces for signal routing.
2. Description of the Related Art
Printed wiring boards are often built of several layers joined together, often by lamination. The surface or top layer usually has surface pads for connecting integrated circuits such as computer chips, memories, etc. These surface pads are usually placed in a pattern that matches the connectors on an integrated circuit to be mounted on the printed wiring board. The surface pads are most often placed in arrays, as will be seen below with respect to
FIGS. 2A and 2B
.
To make connections between various components mounted on the printed wiring board, signal traces link the surface pads with power, ground, etc. As there are often more signal traces than can be reasonably manufactured on only the surface layers, vias are used to connect signal traces placed on various internal layers to the surface layers. To lower infrastructure costs by following industry standard practices, the vias are usually placed in the same uniform array pattern as the surface pads, with rows and columns of vias. The vias connect to the surface pads on the surface layer and are additionally connected as needed to various signal traces on the other layers.
As the number of layers increases, the cost of manufacturing the printed wiring board increases. To decrease the number of layers used, the number of signal traces between the vias may be increased, that is, instead of a single signal trace between each pair of rows or columns, two or more signal traces are placed. Since the vias normally comprise a uniform array with pitch spacing set by agreement or industry standards to correspond to the surface pads, placing two signal traces instead of one signal trace requires that the two signal traces be thinner, i.e. have a smaller width. A signal line must have a certain minimum width for the signal trace to be manufacturable with a high degree of reliability. The thinner the signal trace, the more expensive the signal trace is to manufacture. So building printed wiring boards with more layers may prove less expensive, in some instances, than building fewer layers with thinner signal traces.
Integrated circuit packaging may now include technology originally designed for printed wiring boards. For example, some integrated circuits include what is, in essence, a miniature printed wiring board between the semiconductor itself and the plastic or ceramic packaging, which encases and protects the semiconductor. This miniature printed wiring board converts the signal outputs of the semiconductor to the connector pinout that corresponds to the printed wiring board pads. What is needed is a way to build electrical interconnection devices, such as semiconductor packages and printed wiring boards, less expensively while providing sufficient signal traces.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an apparatus and system comprising electrical interconnection devices, such as printed wiring boards, semiconductor packages, and printed circuit boards, having novel via and signal trace positioning. In one embodiment, the vias are repositioned off-center from the pattern of the surface pads, while the surface pads remain in their desired pattern. This embodiment may advantageously increase signal trace routing density. In another embodiment, via groups, also referred to as staircase vias, connect surface pads with vias extending into the electrical interconnection device. The via groups preferably convert the pad geometry on the surface to a more open via pattern on one or more internal layers. These embodiments may advantageously increase signal trace routing density, which may allow for the electrical interconnection device to have fewer layers, yet still maintain ease and cost of manufacturability.
A first embodiment includes a printed wiring board upon which a semiconductor package is to be mounted. The printed wiring board comprises a plurality of pads formed on a surface of the printed wiring board for providing electrical connections to the semiconductor package and a plurality of vias each extending from a corresponding pad to another layer of the printed wiring board. A related embodiment includes a semiconductor package for mounting upon a printed wiring board. The semiconductor package comprises a plurality of pads formed on a surface of the semiconductor package for providing electrical connections to the printed wiring board and a plurality of vias each extending from a corresponding pad to another layer of the semiconductor package. In both embodiments, each of the plurality of vias is offset from a central location of its corresponding pad. This feature may advantageously allow for greater spacing between various vias, allowing more signal traces to be placed therebetween. Additional related embodiments include a printed circuit board comprising a printed wiring board with an integrated circuit attached. Either or both of the printed wiring board and integrated circuit include a via offset from a central location of its corresponding pad.
A further embodiment is contemplated that includes a via group comprising a plurality of vias. In one implementation, a first via connecting a surface of the electrical interconnection device to a first inner layer electrically connects a pad on a surface of the electrical interconnection device to a second via. The second via extends from the first inner layer to a second layer of the electrical interconnection device. The centers of the first via and the second via are non-collinear. This feature may advantageously allow for inner layers of the electrical interconnection device to have additional space for placing additional signal traces. In a related embodiment, an electrical interconnection device includes a uniformly spaced set of pads on the surface. Via groups, comprising a first set of vias and a second set of vias, extend from the uniformly spaced surface pads. Spacing among the second set of vias is non-uniform. This feature may also advantageously allow for inner layers of the electrical interconnection device to have additional space between vias for placing additional signal traces.
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Freda Michael C.
Hassanzadeh Ali
Ko Han Y.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Potter Roy
Sun Microsystems Inc.
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