Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-10-13
2002-07-23
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S145000
Reexamination Certificate
active
06424189
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a system for event synchronization, and particularly to an apparatus and a system for multi-stage event synchronization which buffers data in data transmissions between an origination agent and a destination agent at different operating frequencies or at equal frequency but different phases.
2. Description of the Related Art
As far as circuit designs are concerned, since the two ends of data transmission between an origination agent and a destination agent operate at different frequencies or at equal frequency but different phases, one end captures data directly transmitted from another end in edge-triggered form will cause errors.
FIG. 1
is a schematic diagram of a prior art event synchronization apparatus, wherein an intermediate agent
11
is situated between an origination agent
14
and a destination agent
15
for buffering the data transmitted between the origination agent
14
and destination agent
15
. The intermediate agent
11
comprises a FIFO (First In First Out)
12
and a control module
13
, wherein the FIFO
12
is a dual-port structure connected to the origination agent
14
and destination agent
15
through a data bus
18
and
18
′ respectively, and the control module
13
is connected to the origination agent
14
and destination agent
15
through a control bus
19
and
19
′ respectively. The FIFO module
12
and control module
13
communicate each other through a producing interface
16
and a consuming interface
17
. The structure in
FIG. 1
operates in two modes. In the first mode, data from the origination agent
14
are transmitted to the FIFO module
12
through the data bus
18
, while in the second mode, the destination agent
15
reads the data stored in the FIFO module
12
through the data bus
18
′. Under the first mode, the origination agent
14
notifies the control module
13
through the control bus
19
of the fact that data will be transmitted, and the control module
13
first examines if the FIFO module
12
is full by the producing interface
16
. If it is full, the control module
13
notifies the origination agent
14
through the control bus
19
to stop transmitting data to the FIFO module
12
. If it is not full, the control module
13
notifies the origination agent
14
through the control bus
19
to transmit data to the FIFO module
12
, and updates the pointer pointing to the next storing location by the producing interface
16
. Under the second mode, the destination agent
15
notifies the control module
13
through the control bus
19
′ of the fact that data will be transmitted, and the control module
13
first examines if the FIFO module
12
is empty by the consuming interface
17
. If it is empty, the control module
13
notifies the destination agent
15
through the control bus
19
′ to stop transmitting data from the FIFO module
12
. If it is not empty, the control module
13
notifies the destination agent
15
through the control bus
19
′ to transmit data from the FIFO module
12
, and updates the pointer pointing to the next reading location by the consuming interface
17
.
FIG. 2
is a schematic diagram of a prior art FIFO module, mainly comprising a producing end
28
, a consuming end
27
and a FIFO buffer
29
. The producing end
28
includes a producing module
24
and a first counter
22
, and connects the producing interface
16
and the FIFO buffer
29
. The producing module
24
is used to generate a rear pointer pointing to the currently storing location, and the first counter
22
is an up-down counter for accumulating the number of buffering data in the FIFO buffer
29
. The consuming end
27
includes a consuming module
21
and a second counter
23
, and connects the consuming interface
17
and the FIFO buffer
29
. The consuming module
21
is used to generate a front pointer pointing to the currently reading location, and the second counter
23
is an up-down counter for accumulating the number of buffering data in the FIFO buffer. When the producing end
28
executes a push event, meaning that the origination agent
14
wants to store data to the FIFO buffer
29
, the producing end
28
first examines the content of the first counter
22
. If the content is equal to a storing maximum, representing the FIFO buffer
29
is full, a “full condition” is issued and the origination agent
14
is notifies to stop transmitting data to the FIFO buffer
29
. If the content is not equal to the storing maximum, the producing module
24
sends the rear pointer to the FIFO buffer
29
and the data from the origination agent
14
are stored in the location the rear pointer points to in the FIFO buffer
29
. Meanwhile, the first counter
22
and the second counter
23
will count up by adding the number of the push events. Likewise, when the consuming end
27
executes a pop event, meaning that the destination agent
15
wants to read data from the FIFO buffer
29
, the consuming end
27
first examines the content of the second counter
23
. If the content is equal to a storing minimum, representing the FIFO buffer
29
is empty, an “empty condition” is issued and the destination agent
15
is notifies to stop transmitting data from the FIFO buffer
29
. If the content is not equal to the storing minimum, the consuming module
21
sends the front pointer to the FIFO buffer
29
and the data to the destination agent
15
are stored in the location the front pointer points to in the FIFO buffer
29
. Meanwhile, the first counter
22
and the second counter
23
will count down by subtracting the number of the pop events. Because the functions of the first counter
22
and second counter
23
are the same, one of them can be neglected. However, since the second counter
23
is used to control the consuming end
27
and the first counter
22
is used to control the producing end
28
, for the sake of module design, both of them are better used.
FIG. 3
is a schematic diagram of a prior art FIFO buffer. The FIFO buffer
29
is used to store and forward the data from the origination agent
14
and to the destination agent
15
, especially when the origination agent
14
and the destination agent
15
operate at different frequencies or at equal frequency but different phases. The mark “*” on an entry of the FIFO buffer
29
represents a sum of useful data are present in the entry. The rear pointer
32
and front pointer
31
represent a starting point and an ending point of a plurality of useful data in the FIFO buffer
29
. When a push event occurs, whether the value of the rear point
32
plus one is equal to the value of the front point
31
is first examined. If the answer is yes, it represents the FIFO buffer
29
is full. If no, representing the FIFO buffer
29
is not full, the rear pointer
32
moves forward one step, meaning that the value of the rear pointer
32
is added by one. When a pop event occurs, whether the value of the front point
31
is equal to that of the front point
31
is first examined. If the answer is yes, it represents the FIFO buffer
29
is empty. If no, representing the FIFO buffer
29
is not empty, the front pointer
31
moves forward one step, meaning that the value of the front pointer
31
is added by one. The accumulation of the rear pointer
32
and front pointer
31
are calculated in modulo. As an example of sixteen entries in the structure of
FIG. 3
, the next value of the rear pointer
32
or front pointer
31
is 0 if the current value is 15.
The structure shown in
FIG. 2
is not suitable for practical use if the origination agent
14
and destination agent
15
operate at different frequencies or at equal frequency but different phases. Under the circumstances, the first counter
22
will misunderstand the number of pop events in the consuming end
27
, and the second counter
23
will misunderstand the number of push events in the producing end
28
. As such, an adequate synchronization circuit should be added to ensu
Chen Tsan-Hui
Lin Chang-Fu
Lin Wen-Hsiang
Su Jen-Pin
Wu Chun-Chieh
Nguyen Linh
Senniger Powers Leavitt & Roedel
Silicon Integrated Systems Corporation
Wells Kenneth B.
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