Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-09-01
2008-11-11
Picardat, Kevin M (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000
Reexamination Certificate
active
07449416
ABSTRACT:
A plasma ashing process for removing photoresist material and post etch residues from a substrate comprising carbon, hydrogen, or a combination of carbon and hydrogen, wherein the substrate comprises a low k dielectric layer, the process comprising forming a plasma from an essentially oxygen free and nitrogen free gas mixture; introducing the plasma into a process chamber, wherein the process chamber comprises a baffle plate assembly in fluid communication with the plasma; flowing the plasma through the baffle plate assembly and removing photoresist material, post etch residues, and volatile byproducts from the substrate; periodically cleaning the process chamber by introducing an oxygen plasma into the process chamber; and cooling the baffle plate assembly by flowing a cooling gas over the baffle plate assembly. A process chamber adapted for receiving downstream plasma, the process chamber comprising an upper baffle plate comprising at least one thermally conductive standoff in thermal communication with a wall of the process chamber; and a lower baffle plate spaced apart from the upper baffle plate.
REFERENCES:
patent: 4341592 (1982-07-01), Shortes et al.
patent: 5364488 (1994-11-01), Minato et al.
patent: 5498308 (1996-03-01), Kamarehi et al.
patent: 5961851 (1999-10-01), Kamarehi et al.
patent: 5968275 (1999-10-01), Lee et al.
patent: 5980638 (1999-11-01), Janos
patent: 6057645 (2000-05-01), Srivastava et al.
patent: 6225745 (2001-05-01), Srivastava
patent: 6281135 (2001-08-01), Han et al.
patent: 6415736 (2002-07-01), Hao et al.
patent: 6630406 (2003-10-01), Waldfried et al.
patent: 2004/0026386 (2004-02-01), Hogan et al.
patent: 2004/0026783 (2004-02-01), Kloster et al.
patent: 2004/0084412 (2004-05-01), Waldfried et al.
patent: 2004/0235299 (2004-11-01), Srivastava et al.
patent: 2005/0150601 (2005-07-01), Srivastava
patent: 2005/0241669 (2005-11-01), Wodecki
patent: 1 150 330 (2001-10-01), None
patent: WO 97/37055 (1997-10-01), None
D. Shamiryan et al., “Low-k Dielectric Materials”, Materials Today, Jan. 2004.,pp. 34-39.
J. Golden et al., “Designing Porous Low-k Dielectrics”, http://www.microbar.com
ews/articles/articles/design LOWkdielectric/porus.htn.
J.T. Rantala et al., “The case for nonporous low-k dielectrics” Solid State Technology, Dec. 2003.
K. Buchanan et al., “Challenges associated with the integration of nanp-porous ultra low k CVD films.”, SEMICON West 2002, SEMI Technical Symposium (STS): Innovations in Semiconductor Manufacturing.
Becknell Alan F.
Ferris David
Hammar Philip
Axcelis Technologies Inc.
Cantor & Colburn LLP
Picardat Kevin M
LandOfFree
Apparatus and plasma ashing process for increasing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and plasma ashing process for increasing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and plasma ashing process for increasing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4022504