Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-09-26
2003-07-29
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
active
06599776
ABSTRACT:
TECHNICAL FIELD
The present invention relates to apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer, suitable for testing, for example, flip chip die, chip scale packages, multi-chip modules, and the like.
BACKGROUND OF THE INVENTION
Bumped die and other bumped devices are widely used throughout the electronics industry. As the drive toward smaller electronics continues, the pitch (or spacing) of solder bumps on such bumped devices continues to decrease. The increasingly finer pitches of the solder bumps on bumped die and bumped devices raise concerns about the reliability of these devices. These concerns are being addressed by testing.
A die (or chip) is typically tested during the manufacturing process to ensure that the die conforms to operational specifications. Solder bumps (or balls) are then formed on bond pads of the die using a solder deposition device, such as a solder ball bumper. The solder bumps are typically formed with a height of from 25 &mgr;m to 75 &mgr;m. The bumped die are then tested by placing conductive test leads in contact with the solder bumps on the die, applying a test signal to the bumps via the test leads, and determining whether the bumped die responds with the proper output signals. If the bumped die tests successfully, it may be installed on a printed circuit board, a chip scale package, a semiconductor module, or other electronics device.
FIG. 1
is a cross-sectional view of a bumped die
10
engaged with a test carrier
20
in accordance with the prior art. In this typical arrangement, the bumped die
10
includes a substrate
12
with a plurality of bond pads
14
thereon. A solder bump
16
(or other suitable conductive material) is formed on each of the bond pads
14
. The test carrier
20
has a plurality of contact pads
22
thereon, each of the contact pads
22
being electrically coupled with a test lead
24
. For testing of the bumped die
10
, the solder bumps
16
engage the contact pads
22
of the test carrier
20
, and the appropriate test signals are applied to the bumped die
10
through some of the test leads
24
. Output signals from the bumped die
10
are monitored through other test leads
24
to determine whether the bumped die
10
is functioning to specifications. Test carrier apparatus of the type shown in
FIG. 1
for testing unpackaged die are described in U.S. Pat. No. 5,519,332 to Wood et. al., incorporated herein by reference.
Testing of the bumped die
10
generally includes four levels of testing. A first or “standard probe” level includes the standard tests for gross functionality of die circuitry. A second or “speed probe” level includes testing the speed performance of the die for the fastest speed grades. A third or “burn-in die” level involves thermal cycling tests intended to drive contaminants into the active circuitry and to detect early failures. And a fourth or “known good die (KGD)” level includes testing to provide a reliability suitable for final products.
To ensure proper transmission of the test signals and output signals, the solder bumps
16
may be temporarily connected with the contact pads
22
by reflowing the bumps, thereby soldering the bumps to the contact pads. After the testing is complete, the solder bumps
16
may be reflowed to disconnect the bumps from the contact pads. Connecting and disconnecting the solder bumps
16
from the contact pads
22
, however, involve time consuming processes and may damage the solder bumps
16
or the contact pads
22
.
Another problem with soldering the solder bumps
16
to the contact pads
22
is that the coefficient of thermal expansion (CTE) of the bumped die
10
may be appreciably different from the CTE of the test carrier
20
. During burn-in die testing, the bumped die
10
and test carrier
20
are placed in a burn-in oven and subjected to temperature cycling (e.g. −55° C. to 150° C.) for a time period of from several minutes to several hours or more. Due to the different CTE of the bumped die
10
and the test carrier
20
and the rigidity of the solder connections, significant stresses may develop throughout the components. These stresses may result in delamination or other damage to the bumped die
16
or the test carrier
20
, and may degrade or damage the connection between the solder bumps
16
and the bond pads
14
.
An alternate approach to soldering is to simply compress the solder bumps
16
into engagement with the contact pads
22
. Ideally, only a small compression force is needed to engage the solder balls
16
against the contact pads
22
so that tests may be conducted. Methods and apparatus for testing die in this manner are fully described in U.S. Pat. No. 5,634,267 to Farnworth and Wood, incorporated herein by reference. The applied compression force, however, must be kept to a minimum because larger forces may damage the circuitry of the bumped die
10
or the test carrier
20
.
A problem common to both the solder reflow and the compression force methods of engagement is that the solder bumps
16
are not uniformly shaped. As shown in
FIG. 1
, the solder bumps
16
are usually of different heights. Using typical manufacturing methods and solders, the nominal variation between the tallest and shortest bumps (shown as a distance d on
FIG. 1
) is presently about 10% of the average solder ball height. Therefore, when the bumped die
10
is placed on the test carrier
20
, the shorter solder bumps may not touch the corresponding contact pads. In some cases, especially for very fine pitch solder bumps, the gaps between the shorter solder bumps and the contact pads may be too large to overcome using solder reflow (because of the small volume of solder in each bump) or by using compression force (because of possible damage to the bumped die).
The variation in solder bump height also creates uncertainty in the final assembly of electronics components that include bumped devices. As the number of bumps on the bumped device increases, the failure rate of the assembled package increases due to solder bump non-uniformity.
FIG. 2
is a partial cross-sectional view of the bumped die
10
of
FIG. 1
engaged with another conventional test carrier
40
. The test carrier
40
includes a test substrate
42
having a plurality of pockets
44
disposed therein. As shown in
FIG. 2
, the pockets
44
have sloping sidewalls
46
, and a pair of contact blades
48
project from opposing sidewalls
46
into each pocket
44
. Conductive test leads
50
are formed on the test substrate
42
, including on the sidewalls
46
and contact blades
48
of the pockets
44
.
During testing, the solder bumps
16
at least partially engage the pockets
44
of the test carrier
40
with the sharp contact blades
48
partially penetrating the solder bumps
16
. The solder bumps
16
may also contact the sloping sidewalls
46
of the test carrier
40
. Thus, the desired electrical connection between the solder bumps
16
and the test leads
50
may be achieved despite the variation in the solder bump height.
Although the test carrier
40
having pockets
44
with contact blades
48
addresses solder bump height variation, testing solder bumps with the test carrier
40
has several disadvantages. For example, because the contact blades
48
penetrate the solder bumps
16
, the solder bumps may be cracked, chipped, or otherwise damaged by the contact blades. The solder bumps
16
may also become stuck to the contact blades
48
, requiring additional time and effort to disengage the bumped die
10
from the test carrier
40
. Furthermore, the test carrier
40
with the plurality of pockets
44
is relatively costly to fabricate and more difficult to maintain than alternative test carriers having flat contact pads.
FIG. 3
is a partial cross-sectional view of the bumped die
10
of
FIG. 1
engaged with another prior art test carrier
60
. In this example, the test carrier
60
includes a test substrate
62
having a plurality of pedestals
64
formed thereon. Test leads
66
are disposed o
Akram Salman
Farnworth Warren M.
Wood Alan G.
Coleman William David
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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