Apparatus and methods for testing a microprocessor chip using de

Details Apparatus and methods for testing a microprocessor chip using de Apparatus and methods for testing a microprocessor chip using de

1996-09-19

2000-02-22

Palys, Joseph

Excavating

371 2231, G06F 1100, G01R 31318

Patent

active

06028983&

ABSTRACT:
A test apparatus and method for design verification of at least one microprocessor chip includes a compatible Joint Task Action Group (JTAG) terminal for access to a plurality of computer functional units contained in the chip. A test input terminal included in the JTAG terminal receives a scan string, the string being coupled to each computer functional unit through a first multiplexer. The scan input string is separated by the JTAG terminal under program control into a series of dedicated scan strings, each dedicated scan string being supplied to a selected functional unit through the first multiplexer. Each functional unit includes start and stop scan clocks for testing the functional under program control using the dedicated scan train for the functional unit. A test output terminal included in the JTAG terminal is coupled to each functional unit through a second multiplexer. The test results of the dedicated scan string under control of the scan clock are supplied to the output terminal through the second multiplexer. The compatible JTAG terminal includes further elements for controlling the scan clocks to select a targeted functional unit for testing purposes while the scan strings for non-targeted functional units remain in an inactive state.

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Bleeker et al., "Boundary Scan Test, a Practical Approach", 1993, pp. 78-81 .

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