Apparatus and methods for performing arithimetic operations on v

Details Apparatus and methods for performing arithimetic operations on v Apparatus and methods for performing arithimetic operations on v

1997-09-05

1999-12-14

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708517, G06F 1716

Patent

active

060030585

ABSTRACT:
A multiply-multiply-accumulate (MMA) system (10) efficiently evaluates matrix products X=F*C. Matrix C is dissected into submatrices A and B taking advantage of symmetry in C. LOG unit (14) converts B, A, and F to LOG values B', A' and F'. These are summed in K parallel calculating units CU's (18) and converted back to Normal domain as P=F*B*A in ALOG units (22) and sent to accumulators ACU's (24). The ACU's (24) accumulate the results. An output buffer (26) combines the results. The B', A' values (32,34) are held in a cache memory (20) and the LOG sums are performed in two steps with intermediate storage.

REFERENCES:
patent: 5301342 (1994-04-01), Scott
patent: 5325215 (1994-06-01), Shibata et al.
patent: 5771391 (1998-06-01), Lloyd et al.

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