Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2009-03-16
2011-12-20
Smith, Zandra (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S015000, C257S018000, C257SE29069
Reexamination Certificate
active
08080820
ABSTRACT:
Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.
REFERENCES:
patent: 5268582 (1993-12-01), Kopf et al.
patent: 5284782 (1994-02-01), Jeong et al.
patent: 7485536 (2009-02-01), Jin
patent: 2003/0080331 (2003-05-01), Ono et al.
patent: 2007/0257301 (2007-11-01), Allibert et al.
patent: 2008/0157058 (2008-07-01), Hudait
patent: 2008/0237573 (2008-10-01), Jin
patent: 2010/107571 (2010-09-01), None
patent: 2010/107571 (2011-01-01), None
Pillarisetty, Ravi, et al., “Apparatus and Methods for Forming a Modulation Doped Non-Planar Transistor”, U.S. Appl. No. 12/319,097, filed Dec. 30, 2008.
International Search Report and Written Opinion received for PCT Patent Application No. PCT/US2010/025845, mailed on Sep. 28, 2010, 8 pages.
Chau Robert
Chu-Kung Benjamin
Hudalt Mantu
Jin Been-Yih
Pillarisetty Ravi
Intel Corporation
Patton Paul
Smith Zandra
Winkle, PLLC
LandOfFree
Apparatus and methods for improving parallel conduction in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and methods for improving parallel conduction in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and methods for improving parallel conduction in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4269434