Apparatus and methods for bus arbitration in a multimaster syste

Details Apparatus and methods for bus arbitration in a multimaster syste Apparatus and methods for bus arbitration in a multimaster syste

1996-01-18

1997-11-18

Sheikh, Ayaz R.

395730, 395287, G06F 1336

Patent

active

056896573

ABSTRACT:
A bus arbitration method for a multimaster system comprising a plurality of masters sharing a global data bus and a plurality of bus arbiters sharing a global identification bus. Each active bus arbiter applies to the identification bus a bus request signal containing a k-bit-wide identification word representative of the priority of the master associated with the bus arbiter. In each prioritization step of the bus grant cycle, a logic level is produced on the identification bus by logically combining bits of equal significance. This logic level is then compared with the corresponding bits of the applied identification words. The k bits of the identification words of the bus arbiters are placed on the identification bus on a time-graded basis; in each prioritization step of the bus grant cycle, only those bits of the identification words are placed on the identification bus which are of equal significance, and in each prioritization step of the bus grant cycle, those bus arbiters whose identification word bit in the prioritization step does not match the logic level of the identification bus are eliminated from the bus arbitration of the bus gram cycle.

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