Apparatus and methods for a physical layout of...

Details Apparatus and methods for a physical layout of... Apparatus and methods for a physical layout of...

2011-03-22

2011-03-22

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C714S764000, C714S773000, C711S104000, C711S170000, C711S173000, C711S211000, C710S107000, C710S305000

Reexamination Certificate

active

07911819

ABSTRACT:
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

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