Apparatus and methods for a high-voltage latch

Details Apparatus and methods for a high-voltage latch Apparatus and methods for a high-voltage latch

2011-01-04

2011-01-04

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C365S189050

Reexamination Certificate

active

07863959

ABSTRACT:
Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.

REFERENCES:
patent: 5298816 (1994-03-01), Kaplinsky
patent: 5629643 (1997-05-01), Moughanni et al.
patent: 6107852 (2000-08-01), Durham et al.
patent: 6157577 (2000-12-01), McPartland
patent: 6188246 (2001-02-01), Ogawa
patent: 6288586 (2001-09-01), Ahn et al.
patent: 6380781 (2002-04-01), Karnik et al.
patent: 6459301 (2002-10-01), Hidaka
patent: 6501315 (2002-12-01), Nguyen
patent: 6621318 (2003-09-01), Burr
patent: 6700412 (2004-03-01), Takahashi
patent: 7369446 (2008-05-01), Chan et al.
patent: 7542347 (2009-06-01), Hanzawa et al.
patent: 2001/0028581 (2001-10-01), Yanagisawa et al.
patent: 2004/0135611 (2004-07-01), Tohsche
patent: 2004/0214389 (2004-10-01), Madurawe
patent: 2006/0171194 (2006-08-01), Lowrey et al.
patent: 2007/0159873 (2007-07-01), Boemler
patent: 2008/0054973 (2008-03-01), Chan et al.
patent: 2008/0056020 (2008-03-01), Chan et al.
patent: WO-2008030812 (2008-03-01), None
patent: WO-2008030812 (2008-03-01), None
“PCT Application No. PCT/US07/77542, International Search Report mailed Mar. 7, 2008”, 3 pgs.
“PCT Application No. PCT/US07/77542, Written Opinion mailed Mar. 7, 2008”, 5 pgs.
Nakagome, Y., et al., “Review and Future Prospects of Low-Voltage RAM circuits.”,IBM Journal of Research and Development, vol. 47(5-6), (Sep. 2003), 525-552.
“U.S. Appl. No. 11/470,536, Final Office Action mailed May 8, 2009”, 15 pgs.
“U.S. Appl. No. 11/470,536, Non Final Office Action mailed Nov. 1, 2007”, 12 pgs.
“U.S. Appl. No. 11/470,536, Non-Final Office Action mailed May 12, 2008”, 11 pgs.
“U.S. Appl. No. 11/470,536, Non-Final Office Action mailed Nov. 25, 2008”, 13 pgs.
“U.S. Appl. No. 11/470,536, Preliminary Amendment mailed Sep. 11, 2007”, 8 pgs.
“U.S. Appl. No. 11/470,536, Response filed Feb. 25, 2008 to Non Final Office Action mailed Nov. 1, 2007”, 13 pgs.
“U.S. Appl. No. 11/470,536, Response filed Feb. 25, 2009 to Non-Final Offce Action mailed Nov. 25, 2008”, 14 pgs.
“U.S. Appl. No. 11/470,536, Response filed Sep. 12, 2008 to Non-Final Office Action mailed May 12, 2008”, 10 pgs.

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