Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-04-26
2001-03-13
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090, C365S185230, C365S185240
Reexamination Certificate
active
06201737
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of flash memory devices. More particularly, the invention relates to a mechanism and method to characterize the threshold distribution in an NROM virtual ground array.
BACKGROUND OF THE INVENTION
The overall array architecture for a typical virtual ground array based flash memory device includes a virtual ground array accessed by a set of row decoders/multiplexors and a set of column decoders/multiplexors. The virtual ground array contains information stored in individual memory elements. The row decoders/multiplexors are used to access specific memory elements within each memory block and the column decoder/multiplexor provides the input and output circuitry for each memory element.
The architecture of a virtual ground array comprises both individual memory elements and select gates. The memory elements are embodied in non-volatile transistors that may be programmed to a logic state of 0, 1, or other states depending on the particular type of transistor and programming used. The select gates are embodied in normal MOSFETs. Selectable word lines address both the control gates of the transistors that comprise the individual memory elements and select gates in the virtual ground array. Sets of memory elements are connected in series along each word line. The select gates are connected in pairs that are coupled to alternate select gate address lines. The pairs of select gates are connected with pairs of memory elements and a global bitline. A set of multiplexors control the columns that are connected to the external circuitry, such as the sensing circuitry and data-in path. The multiplexors are controlled by a set of column address decoders. Thus, the decoders and multiplexors regulate the flow of data into and out of the virtual ground array.
Variations of the threshold voltage of the individual memory elements within the virtual memory array occur as a result of variations in the manufacture, continual operation over time and as a result of operating conditions of the memory device. Because of these variations in the threshold voltage, it is necessary to characterize the distribution and placement of the threshold voltages for both reasons of functionality and reliability.
A safe and accurate sensing scheme uses sensing from the source side of the virtual ground array. Sensing is accomplished from the source side as using the drain side of the virtual ground array has a number of disadvantages. The main disadvantage of drain side sensing is that all the other bitlines connected with memory elements not being sensed must be precharged to the drain voltage or higher before the sensing routine commences. Precharging the bitlines, in this case, uses both time and power. Time is necessary to initiate, perform, and verify the precharging sequence when sensing from the drain side. Excess power is consumed in each of the precharge steps as well, for example decreasing battery lifetime for any portable electronics unit using the virtual ground array. In addition, sensing from the drain side leads to larger leakage currents and more thus error. Thus, it is necessary to characterize the threshold distribution of memory elements using the source side to determine the optimal operating conditions.
BRIEF SUMMARY OF THE INVENTION
In view of the above, a mechanism and method of characterizing the distribution and placement of threshold voltages for individual flash memory elements in a virtual ground array is provided.
A first aspect of the present invention is directed to a method for characterizing non-volatile memory elements in a virtual ground array from the source side. The method comprises selecting a set of memory elements contained in the virtual ground array. External control exists for at least one voltage input to at least the gate, drain, or source of at least one selected memory element in the set of selected memory elements. The current from the source of the selected memory element is determined.
An aspect of the present invention includes determining the current at the source of the selected memory element. The determination may comprise changing the voltage applied to the gate of the selected memory element incrementally toward a predetermined voltage while holding the voltage applied to the drain constant or changing the voltage applied to the drain incrementally while holding the voltage applied to the gate constant. In addition, both the gate and drain voltages may be changed simultaneously. The voltages may be changed until predetermined voltages are applied or the memory element is otherwise fully characterized. The method includes providing at least one operational element adapted to pass externally controlled near ground voltages to the selected memory element. The method may be repeated until all of the memory elements in a set of selected memory elements have been characterized.
A second aspect of the present invention is directed towards an apparatus for characterizing non-volatile memory elements in a virtual ground array from the source side. The apparatus comprises a virtual ground array containing memory elements, at least one source multiplexor, at least one word line multiplexor, and at least one drain multiplexor. Each of the memory elements contained in the virtual ground array is selectable by a gate, source, and drain. The gate of the memory element is selectable by a word line of a plurality of word lines, the source is selectable by a first bitline of a plurality of bitlines, and the drain is selectable by a second bitline of the plurality of bitlines.
Each source multiplexor is operatively connected with the source of a selected memory element contained in the virtual ground array through another multiplexor. The source multiplexor multiplexes the source to either internal sense circuitry or an I/O pad. The I/O pad is in communication with external sense circuitry. Each drain multiplexor is operatively connected with the drain of a selected memory element contained in the virtual ground array through another multiplexor. The drain multiplexor multiplexes the drain to either an internal drain voltage generator or an external drain controller. Each word line multiplexor is operatively connected with the gate of a selected memory element contained in the virtual ground array through a decoder. The word line multiplexor multiplexes the gate to either an internal gate voltage generator or an external gate controller. The drain, source, and the gate of a selected memory element may be externally controlled and the current from the selected memory element is determined. At least one operational element is adapted to pass externally controlled near ground voltages to the selected memory element.
The apparatus may further comprise an external gate controller operative to apply a gate voltage to the gate of the selected memory element and an external drain controller operative to control either the drain voltage. The gate voltage can be incrementally changed toward a predetermined voltage and the drain voltage held constant. Alternatively, the drain voltage can be incrementally changed toward a predetermined voltage and the gate voltage held constant or any combination thereof. In any case, the current from the source of the selected memory element is determined after each incremental change. The voltages may be changed until predetermined voltages are applied or the memory element is otherwise fully characterized. The characterization continues until the characteristics of all of a predetermined set of memory elements in the virtual ground array have been determined.
The apparatus further comprises select gates, selectable by select gate lines, local bitlines formed by a diffusion process and connecting the select gates with the memory elements, and global bitlines composed of metal and connecting the select gates with elements external to the virtual ground array. The memory elements are selectable by word lines and at least two of the select gates.
It is therefore a primary advantage of the pre
Hollmer Shane
Kurihara Kazuhiro
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Nguyen Tan T.
LandOfFree
Apparatus and method to characterize the threshold... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method to characterize the threshold..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method to characterize the threshold... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2531415