Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2006-11-21
2006-11-21
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080, C365S233100, C365S185230
Reexamination Certificate
active
07139215
ABSTRACT:
A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.
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Asano Toru
Dhong Sang Hoo
Nakazato Takaaki
Takahashi Osamu
Carr LLP
Elms Richard
Gerhardt Diana R.
Wendler Eric J.
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