Apparatus and method of supporting functional design of logic ci

Details Apparatus and method of supporting functional design of logic ci Apparatus and method of supporting functional design of logic ci

1995-12-27

1998-05-12

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, 364578, G06F 1560

Patent

active

057515921

ABSTRACT:
By means of tables, characters, and the like displayed on the screen of a CRT monitor, a functional diagram editor element can generate, on the screen of the CRT monitor, a functional diagram for representing the operation of a logic circuit. A functional diagram check element detects the presence or absence of a contradiction in the generated functional diagram. Furthermore, a functional simulation element can perform the functional verification of the functional diagram free from contradiction. A hardware-description-language conversion element can generate a hardware description language from the functional diagram in which the circuit operation has undergone error correction. A logic synthesis element can generate netlist information from said hardware description language.

REFERENCES:
patent: 4510572 (1985-04-01), Reece et al.
patent: 4566064 (1986-01-01), Whitaker
patent: 4695968 (1987-09-01), Sullivan, II et al.
patent: 4855726 (1989-08-01), Nishio
patent: 4891773 (1990-01-01), Ooe et al.
patent: 4916627 (1990-04-01), Hathaway
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5051938 (1991-09-01), Hyduke
patent: 5202841 (1993-04-01), Tani
patent: 5212650 (1993-05-01), Hooper et al.
patent: 5222029 (1993-06-01), Hooper et al.
patent: 5224055 (1993-06-01), Grundy et al.
patent: 5243538 (1993-09-01), Okuzawa et al.
patent: 5287289 (1994-02-01), Kageyama et al.
de Lange et al., "A Hierarchical Constraint Graph Generation and Compaction System For Symbolic Layout", IEEE, pp. 532-535, 1989.
Feng et al., "Single Multiple-Values PLA's and the Design of Fast Multiple-Valued Arithmetic Operation Units for Systolic MV-DTW Processor," IEEE, 1991, pp.2216-2219.
Choon B. Kim "Multiple Mixed-Level HDL Generation From Schematics For Asic Design" IEEE pp. 8-2.1-2.4, Aug. 1991.
XJ Wang "Behavioral VHD1 Code Generation For Synchronous FSM's " IEEE pp. 529-532, Feb. 1992.
Nikkei Electronics, No. 565, SPeeDChART-VHDL, Oct. 12, 1992, p. 239.

Affiliated with

Also associated with

Rating

Apparatus and method of supporting functional design of logic ci does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method of supporting functional design of logic ci, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method of supporting functional design of logic ci will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-988892