Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
1997-11-14
2002-08-06
Chin, Wellington (Department: 2664)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S470000
Reexamination Certificate
active
06430198
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data communications and more particularly relates to an apparatus for and method of counting the length of data packets.
BACKGROUND OF THE INVENTION
The use of packets to transmit data from one place to another is in widespread use today in the field of data communications. The transmission of data encapsulated into packets is common throughout the networking field. Network devices such as switches and routers typically operate on data packets having a known length or size. Within these network computer devices the data packet input typically passes several decision points during the switching and/or routing process. At each of these decision points, the end of the data packet must be determined using some form of counting function. This counting function is typically performed at each and every decision point in the system, wherever the length of the packet needs to be known. The need to constantly and repeatedly count the length of the packet is very wasteful in terms of processing resources and in terms of hardware requirements. The increased processing demands and circuit complexity translates to higher product cost which is a major disadvantage in today's highly competitive market.
A more detailed example of a prior art network computing device is given below to better illustrate the problems associated with the prior art. A high level block diagram illustrating an example prior art switching/routing device incorporating multiple packet length counting processes is shown in FIG.
1
. The prior art device, generally referenced
12
, comprises a plurality of processing units
19
numbered 1 through N. Each processing unit comprises a packet data processor
14
and a packet length processing unit
16
. The packet data processors
14
are connected together sequentially in daisy chain fashion. Similarly, the packet length processing units
16
are connected together sequentially in daisy chain fashion. The input data packet is input to the packet data processor in processing unit #
1
as indicated in FIG.
1
and proceeds through multiple decision points or points of processing throughout the network device.
For illustration purposes
FIG. 1
shows the first and second processing point up to and including the N
th
processing point. Also input to the network computing device is a start of packet signal. The start of packet (SOP) signal is input to the packet length processing unit
16
in processing unit #
1
and is daisy chained from one packet length processing unit to the next packet length processing unit. In addition, the SOP signal is generated as an output signal from the packet length processing unit
16
in processing unit #N to be used by network equipment located downstream.
Note that the packet length processor in each processing unit functions to generate the start of packet signal for the downstream processing units. In addition, the length counter functions to generate an end of packet (EOP) signal at any point along the packet length. For example, the packet length processor can generate the EOP one, two or three bytes before the end of the packet.
A timing diagram illustrating the start of packet signal input to each individual packet length counting processor is shown in FIG.
2
. The signals shown in
FIG. 2
represent two packet times, indicated as Packet A and Packet B. Each of the circled points A through D correspond to the similarly indicated circled points in the circuit of FIG.
1
. Timing trace A represents the packet data input to the packet data processor
14
in processing unit #
1
. Timing trace B represents the SOP signal input to the packet length processor in processing unit #
1
. Timing trace C represents the packet data input to the packet data processor in processing unit #
2
. Timing trace D represents the SOP signal input to packet length processor in processing unit #
2
.
The input data shown in timing trace A comprises, for example, bytes labeled A
1
, A
2
, etc. The data unit may comprise any suitable data length such as a word, byte or bit. The start of packet (SOP) signal at timing trace B, labeled SOP A, is shown active for one data unit within packet A. Packet B follows, comprising bytes B
1
, B
2
, etc. Timing trace B also shows the SOP B signal associated with Packet B.
After a processing delay time, the Packet A data is output by the packet data processor in processing unit #
1
and input to the packet data processor in processing unit #
2
, as represented by timing trace C. Similarly, the SOP A signal is output by the packet length processor in processing unit #
1
after some time delay and input to the packet length processor in processing unit #
2
, as represented by timing trace D. The start of packet (SOP) signal at timing trace D, labeled SOP B, is shown active for one data unit within packet B.
The SOP A signal is processed by the packet length processor
16
in processing unit #
1
and, after some time delay, is output to the packet length processor in processing unit #
2
in synchronization with the packet A date. Each packet length processing unit must individually count the length of the packet received at that decision point within the network computing device. In this example, it is assumed that each data packet processing unit within the net,work computing device must have knowledge of the length of the packet it is processing. Thus, a major disadvantage of prior art circuits is that the length of the packet must be repeatedly calculated at each decision point within the device. Even though the start of packet signal is received by each packet length processing unit along with the data packet, the length of the packet must be separately and individually counted over and over again. This is very inefficient and wasteful in terms of hardware and silicon real estate utilization.
SUMMARY OF THE INVENTION,
The present invention is an apparatus for and a method of reducing the packet length count processing in a network device. Data communication devices such as switching and/or routing devices typically operate on data packets having a certain length. During internal processing of the switch or router the data packet typically passes several decision points where the end of the data packet must be determined using counting functions. The present invention discloses an apparatus for and a method of determining the end of a packet at the ingress point of the switching or routing device using a single counting function. After the counting function verifies the length of the data packet, a signal indicating the length of a data packet is generated. This packet length indicator signal is then propagated throughout the system along with the data packet itself. The packet length indicator signal is then used at all decision points that involve the data packet. The packet length indicator signal itself is generated so as to indicate the start of the data packet in addition to the end of the data packet, thus indicating the length of the packet. This obviates the need for the length of the packet to be counted over and over again in the course of processing the data packet within the network device, e.g., a switch or router.
There is therefore provided in accordance with the present invention a packet length processing apparatus comprising a packet length indicator generator for generating a packet length indicator signal from a start of packet signal input thereto the packet length indicator signal constructed so as to be indicative of the length of the data packet and a regenerator for outputting a regenerated start of packet signal for use by downstream computing devices, the regenerator operative to produce the regenerated start of packet signal from the packet length indicator signal.
The packet length indicator generator comprises a counter for counting up to a value L which is representative of the length of the data packet to be counted, the counter outputting an indication of the current count, de
Glaser Ilan
Moyal Yehuda
3Com Corporation
Chin Wellington
Pham Brenda
Zaretsky Howard
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