Apparatus and method of preventing a deadlock condition in a com

Details Apparatus and method of preventing a deadlock condition in a com Apparatus and method of preventing a deadlock condition in a com

1995-12-07

1998-08-18

Sheikh, Ayaz R.

395280, 395287, 395288, 395289, 395290, 395293, 395299, 395306, 395308, G06F 1314

Patent

active

057970181

ABSTRACT:
Circuitry for tristating the address and data outputs of a processor to prevent a deadlock condition when the processor and another bus master is accessing a shared resource. The processor is located on a local bus and the other bus master is located on a PCI bus. Bi-directional tristate buffers are placed between the address and data output pins of the processor and the address and data portions of the first bus. If the processor is requesting a local-bus-to-PCI-bus cycle, and the PCI bus master is asserting a request for a local bus shared resource, the processor address and data output pins are tristated by the tristate buffers to allow the PCI bus master cycle to proceed. After the PCI bus master cycle completes, the tristate buffers are reenabled to allow the processor cycle to complete.

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