Apparatus and method of orienting asymmetrical semiconductor dev

Details Apparatus and method of orienting asymmetrical semiconductor dev Apparatus and method of orienting asymmetrical semiconductor dev

1995-05-30

1998-05-05

Teska, Kevin J.

Boots, shoes, and leggings

364490, 327427, 327437, 327565, 327566, 257408, 257344, 257366, G06F 1500, H01L 2710

Patent

active

057484759

ABSTRACT:
A computer implemented method provides for orientation and lay-out asymmetrical semiconductor devices. The sources of operating potential (20, 30) are identified. The PMOS transistors (22-28) are combined between the first (more positive) source of operating potential and a common node (12) into a combination block (48). The NMOS transistors (14-18) are combined between the common node and the second (less positive) source of operating potential into another combination block (52). The PMOS source terminals are coupled to more positive potentials, and the PMOS drain terminals are coupled to less positive potentials within the first combination block. The NMOS source terminals are coupled to less positive potentials, and the NMOS drain terminals are coupled to more positive potentials within the second combination block. For transmission gates (60, 62), a driving source is identified and the PMOS and NMOS source terminals are coupled to the driving source.

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patent: 5598347 (1997-01-01), Iwasaki
patent: 5608240 (1997-03-01), Kumagai
A Mixed Asymmetric/Symmetric (Mass) MOSFET Cell for ASIC Kumagi et al, Apr. 1994, IEEE, pp. 116-119.

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