Apparatus and method of minimizing performance degradation of an

Details Apparatus and method of minimizing performance degradation of an Apparatus and method of minimizing performance degradation of an

1996-04-12

1999-02-23

Teska, Kevin J.

395707, G06F 9455

Patent

active

058753184

ABSTRACT:
The invention provides an instruction set translator for translating a source code executable by a first processor to a target code executable by a second processor. The translation of the source code occurs one instruction at a time. The instruction set translator determines, after a first execution of the target code, whether at least one of the instructions is modified. If an instruction is modified, then only this particular instruction is purged from the target code. This is made possible by the use of a hash table to monitor addresses of all modified instructions. If the address of an instruction is in the hash table, it signifies that the instruction has been modified. To isolate the translation of the modified instruction in the target code, the invention will break up the source code translation just before the modified instruction. This allows for the translation of the modified instruction to occur separately. Consequently, each time the instruction is modified only that instruction is purged from the target code.

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