Apparatus and method of maintaining processor ordering in a mult

Details Apparatus and method of maintaining processor ordering in a mult Apparatus and method of maintaining processor ordering in a mult

1996-01-18

1998-05-12

Kim, Matthew M.

395473, 395450, 395457, G06F 1208

Patent

active

057519951

ABSTRACT:
In a computer system having a plurality of processors, an apparatus and method for maintaining processor ordering associated with read and write operations of these processors. When data from a producer processor is initially retired, it is stored in a FIFO buffer internal to that processor. If that processor subsequently wishes access to that data, the data is retrieved from and stored back to the FIFO. The data temporarily stored in the FIFO is used to update a main memory shared by the plurality of processors. This update function occurs only after the data has been globally observed in order to guarantee that if any other processor in the system reads data from the main memory, it will obtain an updated version of that data. This ensures that the processor ordering is maintained with respect to the multiple processors residing within the computer system.

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