Boots – shoes – and leggings
Patent
1994-02-25
1996-08-27
Kim, Matthew M.
Boots, shoes, and leggings
395471, 395473, 395467, 395448, 395469, 364DIG1, 3642318, 36424344, G06F 1208
Patent
active
055510051
ABSTRACT:
In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.
REFERENCES:
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 5297269 (1994-03-01), Donaldson et al.
patent: 5303362 (1994-04-01), Butts, Jr. et al.
patent: 5335335 (1994-08-01), Jackson et al.
Fisch Matthew
Sarangdhar Nitin V.
Wang Wen-Hann
Intel Corporation
Kim Matthew M.
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